DS90LV047ATMTC/NOPB - 400 Mbps LVDS Quad Driver | TI 16-TSSOP
부품 번호: DS90LV047ATMTC/NOPB ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $3.42 | $3.42 |
| 10 | $3.07 | $30.70 |
| 100 | $2.45 | $245.00 |
| 500 | $2.02 | $1,010.00 |
| 1,000 | $1.65 | $1,650.00 |
| 2,500 | $1.38 | $3,450.00 |
DS90LV047ATMTC/NOPB 개요
A line driver in the LVDS family is a transceiver front-end component that converts single-ended logic levels into a low-voltage differential pair, and the DS90LV047A belongs to that LVDS sub-family which also includes line receivers (DS90LV048A), transceivers (DS90LV049), and serializers/deserializers. Within the broader hierarchy of interface ICs, LVDS drivers sit under differential signaling ICs, which themselves sit under interface ICs, then under wired-connectivity ICs, and finally under integrated circuits. The DS90LV047A and companion line receiver DS90LV048A provide an alternative to high-power pseudo-ECL devices, offering CMOS-level power consumption with multi-hundred-megahertz switching speeds.
Key features include four independent drivers with flow-through pinout, typical differential output swing of 350 mV across a 100 ohm load, support for data rates in excess of 400 Mbps (200 MHz toggle rate), and 3.3 V nominal supply operation from 3.0 V to 3.6 V. Flow-through pin ordering simplifies PCB routing by allowing the input on one side and the LVDS output on the opposite side, which reduces layer count and via usage.
The architecture uses a current-mode LVDS driver stage with on-chip termination, providing controlled edge rates, low EMI, and robust common-mode noise immunity. The wide common-mode range on the differential pair and the LVDS standard's inherent noise margin allow reliable transmission over FR-4 backplanes and ribbon cable at lengths exceeding several meters.
Typical applications include LCD display row/column drivers, board-to-board high-speed data links, clock distribution networks, printers and copiers, network switches and routers, and backplane interconnect for telecommunications equipment. The device is also commonly paired with the DS90LV048A quad receiver to form complete LVDS links.
When designing with this device, maintain a 100 ohm differential termination at the receiver end of the pair, place decoupling capacitors close to the VCC pin, and keep differential traces matched within 10 mil to preserve duty-cycle balance and minimize reflections.
This page synthesizes distributor pricing, drop-in TSSOP alternatives, and practical design guidance not found in the manufacturer datasheet.
드롭인 대체품: DS90LV047ATMTC/NOPB — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: DS90LV047ATMTC/NOPB (동일 폼 팩터 및 풋프린트) — 차이점: Lead-Free Status, Package, Protocol, RoHS Status.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
DS90LV047ATMTCX/NOPB
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
DS90LV047ATMTC
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
SN65LVDS047PW
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
DS90LV047AMTC
✅ 드롭인 ⚠️ 사양 미검증📋 참조 대체품 (카탈로그에 없음)
FIN1047MTC
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
DS90LV047ATMTC/NOPB 사양
| 기능 | LVDS Quad Differential Line Driver |
| Number of Drivers/Receivers | 4 / 0 |
| Data Rate (max) | 400 Mbps (200 MHz toggle) |
| Protocol | LVDS (TIA/EIA-644) |
| Supply Voltage (VCC) | 3.0 V to 3.6 V |
| Nominal Supply Voltage | 3.3 V |
| Input Signal Levels | LVTTL / CMOS / TTL |
| Differential Output Voltage (Typical) | 350 mV across 100 ohm load |
| Common-Mode Output Voltage | 1.2 V typical |
| Propagation Delay | 1.4 ns typical / 2.5 ns max |
| 동작 온도 범위 | -40 C to +85 C |
| 패키지 | 16-TSSOP (4.40 mm body width) |
| 실장 유형 | Surface Mount |
| Pinout Style | Flow-through (inputs opposite outputs) |
| MSL 레벨 | 1 (per TI datasheet) |
| RoHS 상태 | Compliant |
| Lead-Free Status | Lead-Free (NOPB suffix) |
DS90LV047ATMTC/NOPB 핀 구성
| 핀 1 | GND — Ground (recommended decoupling via 0.1 uF to VCC) |
| 핀 2 | D1IN — Channel 1 LVTTL/CMOS input |
| 핀 3 | D2IN — Channel 2 LVTTL/CMOS input |
| 핀 4 | GND — Ground |
| 핀 5 | D3IN — Channel 3 LVTTL/CMOS input |
| 핀 6 | D4IN — Channel 4 LVTTL/CMOS input |
| 핀 7 | GND — Ground |
| 핀 8 | EN — Enable (active-high; tie high for normal operation) |
| 핀 9 | D4OUT+ — Channel 4 LVDS non-inverting output |
| 핀 10 | D4OUT- — Channel 4 LVDS inverting output |
| 핀 11 | GND — Ground |
| 핀 12 | D3OUT- — Channel 3 LVDS inverting output |
| 핀 13 | D3OUT+ — Channel 3 LVDS non-inverting output |
| 핀 14 | D2OUT- — Channel 2 LVDS inverting output |
| 핀 15 | D2OUT+ — Channel 2 LVDS non-inverting output |
| 핀 16 | VCC — 3.3 V supply (3.0 V to 3.6 V) |
일반적인 애플리케이션
DS90LV047ATMTC/NOPB 적합 용도: 6 애플리케이션s: Board-to-Board High-Speed Data Link, LCD Display Row/Column Driver Interface, Clock Distribution and Timing Fan-Out, Industrial Printer and Copier Imaging Pipeline, Network Switch and Router Backplane Interconnect, Test and Measurement Equipment Digital Front-End.
Board-to-Board High-Speed Data Link
The DS90LV047ATMTC/NOPB drives four parallel data channels at up to 400 Mbps across board-to-board cable assemblies, making it ideal for digital cross-connect, base-station backplane, and high-speed inter-rack interconnects. Its 350 mV LVDS swing across a 100 ohm differential pair delivers high noise margin with low EMI, allowing reliable transmission over several meters of twisted-pair or controlled-impedance ribbon cable without repeaters. The 16-TSSOP flow-through pinout keeps input and output traces on opposite sides of the IC, simplifying PCB routing and minimizing layer count in dense backplane designs. Per TI datasheet, the device operates from 3.0 V to 3.6 V with typical propagation delay of 1.4 ns, sufficient for parallel 8-bit/10-bit data buses at 200 MHz.
추천
LCD Display Row/Column Driver Interface
The DS90LV047ATMTC/NOPB is widely used as a column-driver interface in LCD panels, TFT displays, and digital signage backplanes where multiple data lanes must traverse a flex cable or long PCB trace between the timing controller and the row/column driver ASICs. Its 400 Mbps per channel capability supports WUXGA and higher resolutions at typical color depths, while the LVDS common-mode range (0.05 V to 2.35 V typical) rejects the switching noise generated by the panel's charge-pump circuitry. The TSSOP package's 4.4 mm body width fits inside the narrow bezel PCBs common in modern flat-panel displays, and the flow-through pinout matches the natural source-sink signal flow.
추천
Clock Distribution and Timing Fan-Out
In telecom, networking, and test-and-measurement equipment, the DS90LV047ATMTC/NOPB serves as a 1-to-4 differential clock fan-out buffer for distributing low-jitter clocks across a backplane. Each of its four LVDS outputs can drive a separate ASIC, FPGA, or ADC, replacing larger ECL/PECL buffers while consuming milliwatts of power per channel rather than tens of milliwatts. The 1.4 ns typical propagation delay and tight driver-to-driver skew make the device well-suited for source-synchronous timing schemes where matched delays matter. Per TI characterization data, the LVDS output's edge rate is well-controlled, minimizing harmonic content that could couple into adjacent analog channels.
추천
Industrial Printer and Copier Imaging Pipeline
Inside industrial printers, copiers, and multifunction imaging devices, the DS90LV047ATMTC/NOPB carries high-resolution scan data between the image sensor, the ASIC processor, and the print engine controller. The four-channel parallel LVDS interface exceeds the throughput required for 600 dpi color scanning at production line speeds, while the industrial -40 C to +85 C operating range covers the warm internal environment of laser printers and the harsh ambient of factory-floor copiers. The flow-through pinout pairs naturally with the layout of image-pipeline ASICs whose inputs enter on one side and outputs exit on the other, reducing via count and improving signal integrity on densely-routed main boards.
추천
Network Switch and Router Backplane Interconnect
Inside enterprise switches, routers, and telecommunications chassis, the DS90LV047ATMTC/NOPB transmits control and data-plane signals between line cards and the switching fabric across the mid-plane backplane. At 400 Mbps per channel, four parallel lanes provide 1.6 Gbps of aggregate bandwidth, suitable for SPI control buses, management interfaces, and lower-speed data paths. LVDS's inherent common-mode rejection eliminates the ground-offset problems that plague single-ended backplane signaling across multi-volt card-to-card potential differences, while the device's CMOS-level power consumption helps chassis designers meet strict thermal budgets. The 16-TSSOP footprint occupies minimal board area on densely populated line cards.
추천
Test and Measurement Equipment Digital Front-End
In oscilloscopes, logic analyzers, and protocol analyzers, the DS90LV047ATMTC/NOPB drives the high-speed digital data path between the acquisition front-end, the FPGA, and the display/processing subsystem. The 400 Mbps per channel rate easily handles serialized ADC output buses, SPI/parallel configuration data, and inter-board trigger signals in mid-range instruments. The device's low propagation delay and tight driver-to-driver skew preserve the timing relationships that test instruments depend on for accurate measurements. Combined with the DS90LV048A receiver, the DS90LV047ATMTC/NOPB forms a complete LVDS link that rejects the digital switching noise ubiquitous in mixed-signal instrument enclosures, ensuring clean data transport alongside sensitive analog front-ends.
추천
추천 제품 요약
엔지니어링 참조 데이터: DS90LV047ATMTC/NOPB — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | DS90LV047ATMTCX/NOPB | DS90LV047ATMTC | SN65LVDS047PW | DS90LV047AMTC | FIN1047MTC |
|---|---|---|---|---|---|---|
| Package | 16-TSSOP (4.4 mm) | 16-TSSOP (4.4 mm) - same | 16-TSSOP (4.4 mm) - same | 16-TSSOP (PW) - same | 16-TSSOP - same | 16-TSSOP - same |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | onsemi |
| Number of Drivers | 4 | 4 | 4 | 4 | 4 | 4 |
| Maximum Data Rate | 400 Mbps (200 MHz) | 400 Mbps | 400 Mbps | 400 Mbps | 400 Mbps | 400 Mbps |
| Supply Voltage | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V |
| Differential Output Swing | 350 mV typical | 350 mV typical | 350 mV typical | 350 mV typical | 350 mV typical | 350 mV typical |
| RoHS Compliance | Yes (NOPB suffix) | Yes (NOPB suffix) | No (non-NOPB) | Yes | Yes | Yes |
| Operating Temperature | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C |
주요 차별점
- Lower power dissipation than legacy ECL/PECL drivers (vs MC100EL16 (PECL equivalent))
- Flow-through pinout for simpler PCB routing (vs DS90LV031 (non-flow-through quad driver))
- Industrial temperature range standard (vs Commercial-grade SN65LVDS31 (0 C to +70 C))
설계 노트
Maintain a 100 ohm differential impedance on the LVDS output traces and place a 100 ohm termination resistor as close to the DS90LV048A receiver inputs as possible. Match the positive and negative trace lengths to within 10 mil to preserve 50 percent duty cycle and minimize common-mode conversion. Use tightly coupled (edge-to-edge) differential routing rather than loosely coupled side-by-side routing, which can couple switching noise from adjacent traces into the LVDS pair.
Place a 0.1 uF ceramic decoupling capacitor within 3 mm of the VCC pin (pin 16) and add a 4.7 uF tantalum or ceramic bulk capacitor near the IC. The TSSOP ground pin (pin 1) should connect to a low-impedance ground plane via a short trace or via farm; avoid using the TSSOP ground pin as the only ground return path. Per TI datasheet recommendations, separate analog and digital grounds are not strictly required because all inputs are digital, but a single solid ground plane is mandatory for 400 Mbps operation.
The 350 mV LVDS differential output requires the receiver to have approximately 100 mV of threshold margin; always verify with the DS90LV048A or equivalent receiver's worst-case input sensitivity over temperature. Avoid stubs on the LVDS traces - route directly from driver output through the 100 ohm termination to the receiver inputs with no branching. For cable lengths exceeding 0.5 m, add a common-mode choke to suppress common-mode noise from the cable shield, and verify compliance with IEC 61000-4-2 ESD if the cable is user-accessible.
Do not leave the EN pin floating - tie it to VCC through a 10 kohm resistor for normal operation, or drive it directly from a logic output for power sequencing. Floating EN can cause the device to power up in an indeterminate state. Also, never exceed the 3.6 V absolute maximum VCC rating; transients above this level can permanently damage the LVDS output stage. When using the legacy DS90LV047ATMTC (non-NOPB), confirm that downstream assembly processes accept lead-based terminations or switch to the /NOPB variant for RoHS compliance.
규정 준수 정보
RoHS compliance indicated by /NOPB suffix per TI part numbering convention. Reach and conflict minerals compliance per TI product page. AEC-Q100 not applicable - this is a commercial/industrial interface IC, not an automotive-qualified part. Halogen-free status not explicitly stated in available data.
