EP1AGX35DF780I5 - Arria GX FPGA, 35K LE, 780-FBGA | Intel
부품 번호: EP1AGX35DF780I5 ✗ 단종| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $185 | $185.00 |
| 10 | $168.5 | $1,685.00 |
| 100 | $149.2 | $14,920.00 |
| 500 | $132.75 | $66,375.00 |
| 1,000 | $118.4 | $118,400.00 |
EP1AGX35DF780I5 개요
An FPGA (Field-Programmable Gate Array) is a reprogrammable semiconductor device containing configurable logic blocks (CLBs), programmable interconnect, and dedicated hard IP such as transceivers, PLLs, and memory controllers. In the broader system hierarchy, the EP1AGX35DF780I5 belongs to the mid-range programmable logic tier - above CPLDs in density and below ASICs in per-unit cost - and serves as a flexible alternative to fixed-function ASSPs in protocols, DSP, and interface bridging applications.
The EP1AGX35DF780I5 integrates 4 full-duplex 3.125 Gbps transceivers (8 channels), 8 PLLs, and 4 DLLs for robust clock management. Hard IP blocks include PCI Express x1/x4 endpoint, multiple SERDES channels, and dedicated DDR/QDR memory controllers. The 90 nm process technology provides a balance between cost and performance for volume deployment.
Programmable power technology allows unused logic and transceivers to enter low-power states automatically, reducing quiescent consumption in static designs. The 780-pin FineLine BGA package (29 mm × 29 mm, 1 mm pitch) is pin-compatible with other EP1AGX family members, enabling PCB reuse when migrating between Arria GX densities.
Typical applications include communication equipment line cards, industrial video processing, PCI Express endpoint adapters, and DSP co-processing in medical imaging. The integrated transceivers and DDR controllers simplify high-speed serial designs while reducing BOM count.
When designing with this device, ensure the Quartus II design tool supports the EP1AGX35 device family and verify transceiver channel assignments against PCB signal-integrity simulation. I/O bank voltages (1.2V/1.5V/1.8V/2.5V/3.3V) must be configured correctly for LVDS and HSTL interfaces.
This page synthesizes distributor inventory, Arria GX family cross-references, and practical Quartus II design notes not consolidated in a single vendor datasheet.
드롭인 대체품: EP1AGX35DF780I5 — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: EP1AGX35DF780I5 (동일 폼 팩터 및 풋프린트) — 차이점: Speed Grade, Package, Process Technology, RoHS Status, Configuration Method.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
EP1AGX50DF780I5
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
EP1AGX20DF780I5N
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
EP1AGX35CF780I6N
✅ 드롭인✓ 재고 있음
$278.75 / 개
데이터시트 보기 →EP1AGX35DF780C6N
✅ 드롭인✓ 재고 있음
$199.5 / 개
데이터시트 보기 →EP1AGX35DF780C6
✅ 드롭인✓ 재고 있음
가격 문의
데이터시트 보기 →EP1AGX35DF780C5N
✅ 드롭인✓ 재고 있음
$198 / 개
데이터시트 보기 →EP1AGX35DF780I5 최대 정격 & 전기적 특성
| Series | Arria GX |
| Family Name | Arria GX FPGA |
| Manufacturer | Intel (formerly Altera) |
| Logic Elements (LE) | 33,740 |
| Embedded Memory | 1,728 Kbits |
| Embedded Multipliers | 35 (18x18) |
| Transceivers | 8 channels (3.125 Gbps) |
| Number of PLLs | 8 |
| Number of DLLs | 4 |
| Process Technology | 90 nm |
| Hard IP | PCI Express x1/x4 endpoint, DDR2/QDRII+/RLDRAM controllers |
| 패키지 | 780-pin FineLine BGA (29 mm × 29 mm, 1.0 mm pitch) |
| 동작 온도 | -40C to +100C (Industrial) |
| Speed Grade | 5 (medium) |
| 실장 유형 | Surface Mount |
| RoHS 상태 | Compliant |
| Design Tool | Quartus II (legacy, Arria GX support) |
| Lifecycle | Not Recommended for New Designs (NRND) |
| Memory Interfaces | DDR2, QDRII+, RLDRAM II |
EP1AGX35DF780I5 780-pin fineline bga (29 mm × 29 mm, 1.0 mm pitch) 핀 구성 가이드
EP1AGX35DF780I5(780-pin fineline bga (29 mm × 29 mm, 1.0 mm pitch) 패키지)의 핀 구성입니다. 이 디지털 IC에는 GPIO, 통신 인터페이스(UART, SPI, I2C), 전원 핀이 포함되어 있습니다. 대체 핀 기능과 구성 옵션은 제조사 데이터시트를 참조하십시오. 임베디드 시스템 설계와 PCB 레이아웃에 필수적입니다.
다음에 대한 상세 핀아웃 데이터 없음: EP1AGX35DF780I5.
다음을 참조하십시오: 데이터시트 전체 핀 구성은 다음을 참조하십시오.
일반적인 애플리케이션
EP1AGX35DF780I5 적합 용도: 6 애플리케이션s: PCI Express Endpoint Adapter, Telecom Line Card Interface Bridging, Industrial Video Processing Pipeline, DSP Co-Processing in Medical Imaging, Serial RapidIO Switch Fabric, Test & Measurement Instrumentation.
PCI Express Endpoint Adapter
The EP1AGX35DF780I5 integrates a hard PCI Express x1/x4 endpoint IP block alongside 8 transceiver channels at 3.125 Gbps, making it ideal for PCIe Gen1 endpoint adapter cards. With 33,740 logic elements and 35 embedded 18×18 multipliers, designers can implement DMA engines, packet-processing pipelines, or DSP accelerators on a single device. The hard IP reduces FPGA resource utilization by approximately 5-10K LEs compared to soft-core PCIe implementations. Industrial temperature grade (-40C to +100C) supports server and embedded computing deployments.
추천
Telecom Line Card Interface Bridging
The EP1AGX35DF780I5 supports CPRI, OBSAI, and custom serial protocols via 8 transceiver channels at 3.125 Gbps. Its hard SERDES, combined with 8 PLLs and 4 DLLs, enables multi-rate clock synthesis for base-station line cards bridging between backhaul optical links and baseband ASICs. The 1,728 Kbit embedded memory buffers protocol frames with deterministic latency. Power-aware Quartus II compilation reduces quiescent power during low-traffic periods, an important consideration for always-on telecom infrastructure.
추천
Industrial Video Processing Pipeline
The EP1AGX35DF780I5's 35 embedded 18×18 multipliers and 1,728 Kbit embedded memory support multi-channel video scaling, color-space conversion, and motion-estimation blocks. Integrated DDR2/QDRII+ memory controllers at up to 300 MHz DDR provide frame-buffer bandwidth. Industrial temperature grade and surface-mount 780-FBGA suit factory-floor video analytics and machine-vision inspection systems where deterministic real-time processing is required.
추천
DSP Co-Processing in Medical Imaging
Medical ultrasound and CT front-ends benefit from the EP1AGX35DF780I5's 35 18×18 multipliers for FIR filtering, FFT butterfly computations, and beamforming. Combined with DDR2 memory controllers streaming digitized RF samples, the device handles 16-channel beamforming at typical medical imaging sample rates. Industrial temperature range and a 780-FBGA footprint support compact medical PCBs where deterministic low-latency signal processing improves image quality. RoHS compliance aligns with medical device environmental regulations.
추천
Serial RapidIO Switch Fabric
With 8 channels at 3.125 Gbps and hard SERDES, the EP1AGX35DF780I5 acts as a Serial RapidIO endpoint or small switch-fabric node in embedded computing clusters. The hard PCI Express block interoperates with SRIO for hybrid backplanes, while 33,740 LEs implement port arbitration, error recovery, and DMA routing. The 780-FBGA package supports the multi-layer PCB stack-up required for 3.125 Gbps channel-loss compliance.
추천
Test & Measurement Instrumentation
The EP1AGX35DF780I5 is well-suited to high-speed protocol analyzers and logic-analyzer probe heads where 8 transceiver channels capture 3.125 Gbps traffic in real time. Its 1,728 Kbit embedded memory buffers protocol bursts for post-trigger analysis, while 35 embedded multipliers accelerate CRC and scrambling computations. Industrial temperature grade and surface-mount 780-FBGA support benchtop and rack-mount test equipment used in lab and production-line QA environments.
추천
추천 제품 요약
엔지니어링 참조 데이터: EP1AGX35DF780I5 — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | EP1AGX50DF780I5 | EP1AGX20DF780I5N | EP1AGX35CF780I6N | EP1AGX35DF780C6N |
|---|---|---|---|---|---|
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Package | 780-FBGA (29 mm, 1.0 mm pitch) | 780-FBGA (29 mm, 1.0 mm pitch) - same | 780-FBGA (29 mm, 1.0 mm pitch) - same | 780-FBGA (29 mm, 1.0 mm pitch) - same | 780-FBGA (29 mm, 1.0 mm pitch) - same |
| Logic Elements (LE) | 33,740 | 50,600 | 21,580 | 33,740 | 33,740 |
| Embedded Memory (Kbits) | 1,728 | 2,448 | 1,209 | 1,728 | 1,728 |
| Embedded Multipliers (18×18) | 35 | 48 | 20 | 35 | 35 |
| Transceivers (3.125 Gbps) | 8 channels | 8 channels | 8 channels | 8 channels | 8 channels |
| Temperature Grade | Industrial (-40C to +100C) | Industrial | Industrial | Industrial | Commercial (0C to +85C) |
| Speed Grade | 5 | 5 | 5 | 6 | 6 |
| RoHS / Lead-Free | Compliant | Compliant | Compliant | Compliant | Compliant |
주요 차별점
- Higher logic density than EP1AGX20DF780I5N in the same package (vs EP1AGX20DF780I5N)
- Lower cost than EP1AGX50DF780I5 when full density is not needed (vs EP1AGX50DF780I5)
- Industrial temperature grade vs commercial-only EP1AGX35DF780C6N (vs EP1AGX35DF780C6N)
- Hard PCI Express endpoint IP versus soft cores in lower-end Cyclone IV GX (vs Cyclone IV GX family)
설계 노트
The EP1AGX35DF780I5 in the 780-FBGA package has a typical theta_JA of approximately 8-12 C/W with proper thermal via array and 4-layer PCB stack-up. For designs operating at >70% utilization with all 8 transceivers active, expect 3-5 W typical dissipation; ensure adequate airflow or a heatsink attachment. Use the Altera PowerPlay early power estimator in Quartus II before final PCB layout.
The 780-pin FineLine BGA uses a 1.0 mm ball pitch on a 30×30 grid with depopulated balls. A 4-layer PCB stack-up with 0.5 oz copper outer layers and dedicated ground/power planes is recommended for transceiver signal integrity. Route each 3.125 Gbps transceiver differential pair with 100 ohm differential impedance, length-matched within 150 mils, and keep total channel loss under 6 dB at 1.5 GHz.
Do not assume Arria GX is supported in the latest Quartus Prime versions - use Quartus II 13.0sp1 or earlier Web Edition with the Arria GX device library installed. Verify transceiver reference-clock jitter meets <1 ps RMS for CPRI/OBSAI compliance. Industrial temp grade parts (I5 suffix) must be ordered explicitly if -40C operation is required; commercial grade (C6 suffix) parts will fail cold-start at sub-zero temperatures.
Configure unused transceiver channels and PLL/DLL blocks to power-down mode in the Quartus II device configuration to minimize quiescent current. The EP1AGX35DF780I5 supports programmable power technology that automatically shuts down unused logic; combined with careful I/O bank voltage selection (1.2V/1.5V/1.8V/2.5V/3.3V), typical designs achieve 30-40% lower power than full-utilization worst case.
규정 준수 정보
RoHS compliant per Altera/Intel product page. Lead-free terminal finish (Pb-free). Not AEC-Q100 qualified (FPGA, not automotive-grade IC). NRND status - new designs should consider Arria V or Cyclone V families.
