EP1AGX35DF780I5 - Arria GX FPGA, 35K LE, 780-FBGA | Intel
MPN: EP1AGX35DF780I5 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $185 | $185.00 |
| 10 | $168.5 | $1,685.00 |
| 100 | $149.2 | $14,920.00 |
| 500 | $132.75 | $66,375.00 |
| 1,000 | $118.4 | $118,400.00 |
Drop-in alternatives for EP1AGX35DF780I5 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP1AGX50DF780I5
✅ Drop-In📋 Reference alternative (not in catalog)
EP1AGX20DF780I5N
✅ Drop-In📋 Reference alternative (not in catalog)
EP1AGX35CF780I6N
✅ Drop-In✓ In Stock
$278.75 / Unit
View Datasheet →EP1AGX35DF780C6N
✅ Drop-In✓ In Stock
$199.5 / Unit
View Datasheet →EP1AGX35DF780C6
✅ Drop-In✓ In Stock
Contact for price
View Datasheet →EP1AGX35DF780C5N
✅ Drop-In✓ In Stock
$198 / Unit
View Datasheet →EP1AGX35DF780I5 Maximum Ratings & Electrical Characteristics
| Series | Arria GX |
| Family Name | Arria GX FPGA |
| Manufacturer | Intel (formerly Altera) |
| Logic Elements (LE) | 33,740 |
| Embedded Memory | 1,728 Kbits |
| Embedded Multipliers | 35 (18x18) |
| Transceivers | 8 channels (3.125 Gbps) |
| Number of PLLs | 8 |
| Number of DLLs | 4 |
| Process Technology | 90 nm |
| Hard IP | PCI Express x1/x4 endpoint, DDR2/QDRII+/RLDRAM controllers |
| Package | 780-pin FineLine BGA (29 mm × 29 mm, 1.0 mm pitch) |
| Operating Temperature | -40C to +100C (Industrial) |
| Speed Grade | 5 (medium) |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
| Design Tool | Quartus II (legacy, Arria GX support) |
| Lifecycle | Not Recommended for New Designs (NRND) |
| Memory Interfaces | DDR2, QDRII+, RLDRAM II |
EP1AGX35DF780I5 780-pin fineline bga (29 mm × 29 mm, 1.0 mm pitch) Pin Configuration Guide
Complete pinout information for EP1AGX35DF780I5 (780-pin fineline bga (29 mm × 29 mm, 1.0 mm pitch) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP1AGX35DF780I5.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EP1AGX35DF780I5 is suitable for 6 applications: PCI Express Endpoint Adapter, Telecom Line Card Interface Bridging, Industrial Video Processing Pipeline, DSP Co-Processing in Medical Imaging, Serial RapidIO Switch Fabric, Test & Measurement Instrumentation.
PCI Express Endpoint Adapter
The EP1AGX35DF780I5 integrates a hard PCI Express x1/x4 endpoint IP block alongside 8 transceiver channels at 3.125 Gbps, making it ideal for PCIe Gen1 endpoint adapter cards. With 33,740 logic elements and 35 embedded 18×18 multipliers, designers can implement DMA engines, packet-processing pipelines, or DSP accelerators on a single device. The hard IP reduces FPGA resource utilization by approximately 5-10K LEs compared to soft-core PCIe implementations. Industrial temperature grade (-40C to +100C) supports server and embedded computing deployments.
Recommended
Telecom Line Card Interface Bridging
The EP1AGX35DF780I5 supports CPRI, OBSAI, and custom serial protocols via 8 transceiver channels at 3.125 Gbps. Its hard SERDES, combined with 8 PLLs and 4 DLLs, enables multi-rate clock synthesis for base-station line cards bridging between backhaul optical links and baseband ASICs. The 1,728 Kbit embedded memory buffers protocol frames with deterministic latency. Power-aware Quartus II compilation reduces quiescent power during low-traffic periods, an important consideration for always-on telecom infrastructure.
Recommended
Industrial Video Processing Pipeline
The EP1AGX35DF780I5's 35 embedded 18×18 multipliers and 1,728 Kbit embedded memory support multi-channel video scaling, color-space conversion, and motion-estimation blocks. Integrated DDR2/QDRII+ memory controllers at up to 300 MHz DDR provide frame-buffer bandwidth. Industrial temperature grade and surface-mount 780-FBGA suit factory-floor video analytics and machine-vision inspection systems where deterministic real-time processing is required.
Recommended
DSP Co-Processing in Medical Imaging
Medical ultrasound and CT front-ends benefit from the EP1AGX35DF780I5's 35 18×18 multipliers for FIR filtering, FFT butterfly computations, and beamforming. Combined with DDR2 memory controllers streaming digitized RF samples, the device handles 16-channel beamforming at typical medical imaging sample rates. Industrial temperature range and a 780-FBGA footprint support compact medical PCBs where deterministic low-latency signal processing improves image quality. RoHS compliance aligns with medical device environmental regulations.
Recommended
Serial RapidIO Switch Fabric
With 8 channels at 3.125 Gbps and hard SERDES, the EP1AGX35DF780I5 acts as a Serial RapidIO endpoint or small switch-fabric node in embedded computing clusters. The hard PCI Express block interoperates with SRIO for hybrid backplanes, while 33,740 LEs implement port arbitration, error recovery, and DMA routing. The 780-FBGA package supports the multi-layer PCB stack-up required for 3.125 Gbps channel-loss compliance.
Recommended
Test & Measurement Instrumentation
The EP1AGX35DF780I5 is well-suited to high-speed protocol analyzers and logic-analyzer probe heads where 8 transceiver channels capture 3.125 Gbps traffic in real time. Its 1,728 Kbit embedded memory buffers protocol bursts for post-trigger analysis, while 35 embedded multipliers accelerate CRC and scrambling computations. Industrial temperature grade and surface-mount 780-FBGA support benchtop and rack-mount test equipment used in lab and production-line QA environments.
Recommended
Recommended Products Summary
Engineering reference data for EP1AGX35DF780I5 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP1AGX50DF780I5 | EP1AGX20DF780I5N | EP1AGX35CF780I6N | EP1AGX35DF780C6N |
|---|---|---|---|---|---|
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Package | 780-FBGA (29 mm, 1.0 mm pitch) | 780-FBGA (29 mm, 1.0 mm pitch) - same | 780-FBGA (29 mm, 1.0 mm pitch) - same | 780-FBGA (29 mm, 1.0 mm pitch) - same | 780-FBGA (29 mm, 1.0 mm pitch) - same |
| Logic Elements (LE) | 33,740 | 50,600 | 21,580 | 33,740 | 33,740 |
| Embedded Memory (Kbits) | 1,728 | 2,448 | 1,209 | 1,728 | 1,728 |
| Embedded Multipliers (18×18) | 35 | 48 | 20 | 35 | 35 |
| Transceivers (3.125 Gbps) | 8 channels | 8 channels | 8 channels | 8 channels | 8 channels |
| Temperature Grade | Industrial (-40C to +100C) | Industrial | Industrial | Industrial | Commercial (0C to +85C) |
| Speed Grade | 5 | 5 | 5 | 6 | 6 |
| RoHS / Lead-Free | Compliant | Compliant | Compliant | Compliant | Compliant |
Key Differentiators
- Higher logic density than EP1AGX20DF780I5N in the same package (vs EP1AGX20DF780I5N)
- Lower cost than EP1AGX50DF780I5 when full density is not needed (vs EP1AGX50DF780I5)
- Industrial temperature grade vs commercial-only EP1AGX35DF780C6N (vs EP1AGX35DF780C6N)
- Hard PCI Express endpoint IP versus soft cores in lower-end Cyclone IV GX (vs Cyclone IV GX family)
Design Notes
The EP1AGX35DF780I5 in the 780-FBGA package has a typical theta_JA of approximately 8-12 C/W with proper thermal via array and 4-layer PCB stack-up. For designs operating at >70% utilization with all 8 transceivers active, expect 3-5 W typical dissipation; ensure adequate airflow or a heatsink attachment. Use the Altera PowerPlay early power estimator in Quartus II before final PCB layout.
The 780-pin FineLine BGA uses a 1.0 mm ball pitch on a 30×30 grid with depopulated balls. A 4-layer PCB stack-up with 0.5 oz copper outer layers and dedicated ground/power planes is recommended for transceiver signal integrity. Route each 3.125 Gbps transceiver differential pair with 100 ohm differential impedance, length-matched within 150 mils, and keep total channel loss under 6 dB at 1.5 GHz.
Do not assume Arria GX is supported in the latest Quartus Prime versions - use Quartus II 13.0sp1 or earlier Web Edition with the Arria GX device library installed. Verify transceiver reference-clock jitter meets <1 ps RMS for CPRI/OBSAI compliance. Industrial temp grade parts (I5 suffix) must be ordered explicitly if -40C operation is required; commercial grade (C6 suffix) parts will fail cold-start at sub-zero temperatures.
Configure unused transceiver channels and PLL/DLL blocks to power-down mode in the Quartus II device configuration to minimize quiescent current. The EP1AGX35DF780I5 supports programmable power technology that automatically shuts down unused logic; combined with careful I/O bank voltage selection (1.2V/1.5V/1.8V/2.5V/3.3V), typical designs achieve 30-40% lower power than full-utilization worst case.
Compliance Information
RoHS compliant per Altera/Intel product page. Lead-free terminal finish (Pb-free). Not AEC-Q100 qualified (FPGA, not automotive-grade IC). NRND status - new designs should consider Arria V or Cyclone V families.
