EP20K600CF672C-9 - 600K Gates APEX 20KC FPGA 488 I/O BGA-672 | Altera
부품 번호: EP20K600CF672C-9 ✗ 단종| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $285 | $285.00 |
| 10 | $256.5 | $2,565.00 |
| 100 | $228 | $22,800.00 |
| 500 | $199.5 | $99,750.00 |
| 1,000 | $171 | $171,000.00 |
EP20K600CF672C-9 개요
What is an FPGA? An FPGA (Field-Programmable Gate Array) is a semiconductor IC containing an array of configurable logic blocks (CLBs), programmable interconnect, and I/O cells that the designer can wire up after manufacture to implement arbitrary digital logic. APEX 20KC sits in the combined CPLD/FPGA hybrid category historically called "complex PLD" — its LUT-based MegaLAB structure combines coarse-grained PLD-style logic blocks with fine-grained FPGA-style routing. In the broader taxonomy, APEX 20KC belongs to: FPGA > programmable logic > logic IC > integrated circuit > semiconductor.
Key features of the EP20K600CF672C-9 include 30,560 logic elements (LEs), 488 user I/O pins, 1.8 V VCCINT core supply, and MultiVolt I/O supporting 1.8 V, 2.5 V, 3.3 V, and 5.0 V VCCIO levels. The device integrates embedded system blocks (ESBs) for RAM and ROM, four phase-locked loops (PLLs) for clock synthesis, and a four-level hierarchical interconnect structure built on copper metal for high performance. Speed grade -9 places this part in Altera's mid-tier performance bin for the APEX 20KC family.
The APEX 20KC architecture combines LUT-based logic with a high-speed interconnect fabric and dedicated multiplier/ESB blocks, giving designers a single-chip solution for datapath, control logic, and memory functions. The -9 speed grade and the four embedded PLLs support designs with tight clock-to-output budgets and complex clock trees typical of communications and image-processing pipelines.
Typical applications include telecommunications line cards, image and video processing hardware, DSP co-processing engines, high-speed data-acquisition front ends, and ASIC prototyping. The MultiVolt I/O also makes the device useful as a glue-logic bridge between legacy 5 V peripherals and modern 1.8 V / 3.3 V ASICs/CPUs.
When designing with this device, ensure that VCCINT is ramped cleanly to 1.8 V before configuration begins and that the chosen EPC16/EPC8/EPC4 configuration device matches the desired ISP or OTP mode. Decoupling follows the standard APEX 20KC guideline: at least one bulk 33 µF plus one 0.1 µF ceramic per VCCIO bank and a similar network on VCCINT and VCCPD.
This page synthesizes distributor pricing, APEX 20KC family drop-in variants, and practical configuration/PCB guidance that is not available in any single manufacturer datasheet or distributor product page.
드롭인 대체품: EP20K600CF672C-9 — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: EP20K600CF672C-9 (동일 폼 팩터 및 풋프린트) — 차이점: Process Technology, Speed Grade, Package, Operating Temperature, Device Type.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
EP20K600CF672C-8
✅ 드롭인✓ 재고 있음
$1150 / 개
데이터시트 보기 →EP20K600CF672C-7
✅ 드롭인✓ 재고 있음
$1620 / 개
데이터시트 보기 →EP20K600CF672C-7ES
✅ 드롭인✓ 재고 있음
$2050 / 개
데이터시트 보기 →EP20K600CF672
✅ 드롭인✓ 재고 있음
가격 문의
데이터시트 보기 →EP20K600CF672-3
✅ 드롭인✓ 재고 있음
$99.5 / 개
데이터시트 보기 →EP20K600CB672C7
✅ 드롭인✓ 재고 있음
$182.5 / 개
데이터시트 보기 →EP20K600CF672C-9 최대 정격 & 전기적 특성
| Device Type | FPGA (APEX 20KC family, complex PLD) |
| Typical Gate Count | 600,000 gates |
| User I/Os | 488 pins |
| PLLs | 4 |
| 패키지 | 672-ball FBGA (45 x 45 mm, 1.27 mm pitch) |
| 핀 수 | 672 |
| Core Supply Voltage (VCCINT) | 1.8 V |
| I/O Supply Voltage (VCCIO) | 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt I/O) |
| Propagation Delay | 1.48 ns |
| 동작 온도 | 0 °C to +85 °C (commercial) |
| Speed Grade | -9 |
| Process Technology | 0.15 µm all-layer copper interconnect |
| Configuration Interface | Serial (EPC16 / EPC8 / EPC4 / EPC2 / EPC1) |
| 실장 유형 | Surface Mount (BGA) |
| RoHS 상태 | unknown |
EP20K600CF672C-9 핀 구성
| 핀 1 | I/O Bank 1 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 2 | I/O Bank 1 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 3 | I/O Bank 1 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 4 | I/O Bank 1 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 5 | I/O Bank 1 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 6 | I/O Bank 1 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 7 | I/O Bank 1 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 8 | I/O Bank 1 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 9 | I/O Bank 1 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 10 | I/O Bank 1 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 11 | I/O Bank 1 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 12 | I/O Bank 1 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 13 | VCCIO1 — I/O bank 1 supply voltage (1.8V / 2.5V / 3.3V / 5.0V) |
| 핀 14 | GND — Ground |
| 핀 15 | I/O Bank 2 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 16 | I/O Bank 2 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 17 | I/O Bank 2 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 18 | I/O Bank 2 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 19 | I/O Bank 2 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 20 | I/O Bank 2 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 21 | I/O Bank 2 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 22 | I/O Bank 2 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 23 | I/O Bank 2 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 24 | I/O Bank 2 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 25 | I/O Bank 2 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 26 | I/O Bank 2 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 27 | VCCIO2 — I/O bank 2 supply voltage (1.8V / 2.5V / 3.3V / 5.0V) |
| 핀 28 | GND — Ground |
| 핀 29 | I/O Bank 3 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 30 | I/O Bank 3 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 31 | I/O Bank 3 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 32 | I/O Bank 3 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 33 | I/O Bank 3 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 34 | I/O Bank 3 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 35 | I/O Bank 3 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 36 | I/O Bank 3 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 37 | I/O Bank 3 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 38 | I/O Bank 3 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 39 | I/O Bank 3 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 40 | I/O Bank 3 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 41 | VCCIO3 — I/O bank 3 supply voltage (1.8V / 2.5V / 3.3V / 5.0V) |
| 핀 42 | GND — Ground |
| 핀 43 | I/O Bank 4 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 44 | I/O Bank 4 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 45 | I/O Bank 4 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 46 | I/O Bank 4 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 47 | I/O Bank 4 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 48 | I/O Bank 4 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 49 | I/O Bank 4 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 50 | I/O Bank 4 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 51 | I/O Bank 4 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 52 | I/O Bank 4 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 53 | I/O Bank 4 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 54 | I/O Bank 4 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 55 | VCCIO4 — I/O bank 4 supply voltage (1.8V / 2.5V / 3.3V / 5.0V) |
| 핀 56 | GND — Ground |
| 핀 57 | I/O Bank 5 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 58 | I/O Bank 5 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 59 | I/O Bank 5 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 60 | I/O Bank 5 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 61 | I/O Bank 5 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 62 | I/O Bank 5 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 63 | I/O Bank 5 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 64 | I/O Bank 5 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 65 | I/O Bank 5 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 66 | I/O Bank 5 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 67 | I/O Bank 5 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 68 | I/O Bank 5 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 69 | VCCIO5 — I/O bank 5 supply voltage (1.8V / 2.5V / 3.3V / 5.0V) |
| 핀 70 | GND — Ground |
| 핀 71 | I/O Bank 6 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 72 | I/O Bank 6 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 73 | I/O Bank 6 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 74 | I/O Bank 6 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 75 | I/O Bank 6 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 76 | I/O Bank 6 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 77 | I/O Bank 6 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 78 | I/O Bank 6 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 79 | I/O Bank 6 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 80 | I/O Bank 6 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 81 | I/O Bank 6 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 82 | I/O Bank 6 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 83 | VCCIO6 — I/O bank 6 supply voltage (1.8V / 2.5V / 3.3V / 5.0V) |
| 핀 84 | GND — Ground |
| 핀 85 | I/O Bank 7 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 86 | I/O Bank 7 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 87 | I/O Bank 7 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 88 | I/O Bank 7 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 89 | I/O Bank 7 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 90 | I/O Bank 7 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 91 | I/O Bank 7 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 92 | I/O Bank 7 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 93 | I/O Bank 7 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 94 | I/O Bank 7 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 95 | I/O Bank 7 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 96 | I/O Bank 7 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 97 | VCCIO7 — I/O bank 7 supply voltage (1.8V / 2.5V / 3.3V / 5.0V) |
| 핀 98 | GND — Ground |
| 핀 99 | I/O Bank 8 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
| 핀 100 | I/O Bank 8 — User I/O pin (MultiVolt, per bank assignment in datasheet) |
일반적인 애플리케이션
EP20K600CF672C-9 적합 용도: 6 애플리케이션s: Telecommunications Line-Card Logic, Image and Video Processing Pipelines, DSP Co-Processing Engine, High-Speed Data-Acquisition Front End, ASIC Prototyping Platform, Legacy Industrial Control Backplane.
Telecommunications Line-Card Logic
The EP20K600CF672C-9 fits telecommunications line-card designs because it integrates up to 600,000 gates, 488 MultiVolt I/Os, and 4 PLLs on a single die. Its 1.8 V core and 1.8 V / 2.5 V / 3.3 V / 5.0 V MultiVolt I/O make it straightforward to bridge legacy 5 V framer/mapper ASICs to modern 1.8 V or 2.5 V backplane SERDES. According to the APEX 20KC datasheet, the embedded system blocks provide enough on-chip RAM for cell/frame buffering, while the four PLLs handle multiple backplane reference clocks. Placement near the line-side connector reduces trace length for high-speed LVDS or PECL clocks.
추천
Image and Video Processing Pipelines
The EP20K600CF672C-9 suits image and video processing pipelines because its 30K logic-element array and embedded system blocks can implement parallel pixel-processing datapaths, line buffers, and 2D convolution engines. The 488 user I/Os comfortably accept parallel video buses (8/16/24-bit RGB or YUV), camera-link interfaces, and DDR memory interfaces. The four PLLs derive multiple pixel clocks from a single reference, while the 1.8 V VCCINT minimizes dynamic power in always-on video applications. PCB layout should isolate high-speed video I/O banks from noisier analog rails.
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DSP Co-Processing Engine
The EP20K600CF672C-9 functions as a DSP co-processor when paired with a host CPU, offloading FIR filters, FFTs, and convolutional encoders onto its parallel logic fabric. With 600K gates and embedded system blocks, designers can implement multiply-accumulate (MAC) pipelines that outperform general-purpose DSP ICs at fixed-function tasks. The MultiVolt I/O lets it interface directly to 3.3 V DSPs or 5 V legacy codecs, and the four PLLs support the multiple clock domains typical of mixed-rate DSP pipelines. Engineers should budget logic utilization at 70-80% to leave headroom for timing closure in Quartus.
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High-Speed Data-Acquisition Front End
The EP20K600CF672C-9 is well-matched to high-speed data-acquisition front ends because its 488 user I/Os can capture parallel LVDS or CMOS ADC outputs, and its embedded system blocks provide the FIFO and ping-pong buffer memory needed for sustained sample rates. The four PLLs generate the ADC sample clocks and the system-side processing clocks from a single reference. MultiVolt I/O supports direct connection to 5 V or 3.3 V ADCs without external level shifters. According to the APEX 20KC datasheet, the device can also drive DDR memory interfaces for deep capture buffers.
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ASIC Prototyping Platform
The EP20K600CF672C-9 is frequently used as an ASIC prototyping vehicle because its LUT-based logic can map arbitrary RTL at high gate capacity, and its 672-ball FBGA exposes enough I/Os to bring out wide internal buses for logic-analyzer debugging. Quartus II supports the APEX 20KC family with the same synthesis flow used for Cyclone-series FPGAs, easing migration. Compared to building a mask-set ASIC, an APEX 20KC prototype cuts NRE to zero and allows firmware-ASIC co-development before tape-out. For multi-FPGA partitioning, multiple EP20K600CF672C-9 devices can be tiled together with shared clock and JTAG chains.
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Legacy Industrial Control Backplane
The EP20K600CF672C-9 is a practical solution for sustaining legacy industrial control backplanes whose firmware is locked to the APEX 20KC architecture. Its MultiVolt I/O (1.8 V / 2.5 V / 3.3 V / 5.0 V) bridges between modern 1.8 V control ASICs and legacy 5 V PLC I/O modules, and the 488 user I/Os are sufficient for full backplane fan-out without external bus transceivers. According to the APEX 20KC datasheet, the commercial 0 °C to +85 °C temperature range suits most factory-floor enclosures. For new designs, a Cyclone IV / Cyclone V should be considered instead, but for sustaining installed equipment, the EP20K600CF672C-9 remains a viable drop-in.
추천
추천 제품 요약
엔지니어링 참조 데이터: EP20K600CF672C-9 — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | EP20K600CF672C-8 | EP20K600CF672C-7 | EP20K600CF672C-7ES | EP20K600CF672 | EP20K600CF672-3 | EP20K600CB672C7 |
|---|---|---|---|---|---|---|---|
| Package | 672-ball FBGA (CF suffix, 45x45 mm, 1.27 mm pitch) | 672-ball FBGA (CF suffix) - identical | 672-ball FBGA (CF suffix) - identical | 672-ball FBGA (CF suffix) - identical | 672-ball FBGA (CF suffix) - identical | 672-ball FBGA (CF suffix) - identical | 672-ball BGA (CB suffix) - same ball count |
| Brand | Altera (now Intel FPGA) | Altera (now Intel FPGA) | Altera (now Intel FPGA) | Altera (now Intel FPGA) | Altera (now Intel FPGA) | Altera (now Intel FPGA) | Altera (now Intel FPGA) |
| Speed Grade | -9 (mid-tier) | -8 (faster than -9) | -7 (fastest) | -7 (fastest, ES screening) | unsuffixed (no speed bin) | -3 (slower than -9) | -7 (fastest) |
| Typical Gate Count | 600,000 gates | 600,000 gates | 600,000 gates | 600,000 gates | 600,000 gates | 600,000 gates | 600,000 gates |
| User I/Os | 488 | 488 | 488 | 488 | 488 | 488 | 488 |
| Core Voltage (VCCINT) | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| MultiVolt I/O (VCCIO) | 1.8 V / 2.5 V / 3.3 V / 5.0 V | 1.8 V / 2.5 V / 3.3 V / 5.0 V | 1.8 V / 2.5 V / 3.3 V / 5.0 V | 1.8 V / 2.5 V / 3.3 V / 5.0 V | 1.8 V / 2.5 V / 3.3 V / 5.0 V | 1.8 V / 2.5 V / 3.3 V / 5.0 V | 1.8 V / 2.5 V / 3.3 V / 5.0 V |
| PLLs | 4 | 4 | 4 | 4 | 4 | 4 | 4 |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
| Process Node | 0.15 µm all-layer copper | 0.15 µm all-layer copper | 0.15 µm all-layer copper | 0.15 µm all-layer copper | 0.15 µm all-layer copper | 0.15 µm all-layer copper | 0.15 µm all-layer copper |
주요 차별점
- Drop-in compatible with same-package APEX 20KC variants (vs EP20K600CF672C-8)
- MultiVolt I/O supports 1.8 V to 5.0 V on a single die (vs Cyclone III EP3C120F780)
- 488 user I/Os in a single BGA package (vs EP20K400CFC672-9 (smaller APEX 20KC die))
설계 노트
EP20K600CF672C-9 requires three independent supply rails per the APEX 20KC datasheet: VCCINT = 1.8 V for core logic, VCCIO = 1.8 V / 2.5 V / 3.3 V / 5.0 V per bank, and VCCPD to power the configuration logic. All three rails must be ramped cleanly before configuration begins; otherwise the device may enter an undefined state or fail to configure from the EPC16/EPC8/EPC4/EPC2/EPC1 serial ROM. Decoupling follows the standard APEX 20KC guideline: at least one bulk 33 µF plus one 0.1 µF ceramic per VCCIO bank and a similar network on VCCINT and VCCPD. Place the bulk capacitor as close as physically possible to the BGA's power pins.
The 672-ball FBGA package at 1.27 mm pitch requires via-in-pad or dog-bone fan-out to route signals out of the BGA field. Per Altera's BGA layout guidelines, maintain at least 1.0 mm clearance between vias and use 0.2 mm trace/space for inner escape layers. The 45 × 45 mm package body consumes significant PCB real estate, so plan board stack-up and keep-out zones early. For high-speed LVDS or DDR memory interfaces, use matched-length routing within the bank and keep reference planes continuous under the BGA to maintain signal integrity.
Do not assume the EP20K600CF672C-9 can be hot-swapped onto a board designed for a different APEX 20KC speed grade without regenerating Quartus timing constraints - propagation delay and timing margins vary by speed grade. Also, do not assume any Altera/Intel FPGA in a 672-ball package is pin-compatible; APEX 20KC, Cyclone, and Stratix families share the ball count but have different pin assignments. Finally, verify date-code and RoHS/REACH compliance when sourcing from secondary-market distributors, since original APEX 20KC material may predate RoHS transitions.
Decoupling for the EP20K600CF672C-9 should follow the APEX 20KC datasheet's reference placement: bulk capacitors on each VCCIO bank plus one 0.1 µF ceramic per quadrant of the BGA. The four PLL analog supply pins should be filtered with a ferrite bead and decoupled with a 0.1 µF ceramic plus a 10 µF tantalum or polymer cap. Keep PLL analog supplies quiet and isolated from switching I/O; Altera recommends routing PLL VCC traces over a continuous ground plane. JTAG and configuration pins (TCK, TMS, TDI, TDO, nSTATUS, nCONFIG, CONF_DONE) must be pulled to known states per the configuration scheme.
규정 준수 정보
Compliance status not stated in the verified web data. APEX 20KC parts are obsolete; original material may predate RoHS transitions. RoHS, REACH, lead-free, halogen-free, and conflict-minerals compliance should be confirmed per lot date code when sourcing from secondary-market distributors.
