EP910DC-40 - 24-Macrocell UV EPLD, 25 MHz, DIP-40 | Altera
부품 번호: EP910DC-40 ✗ 단종| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $24.75 | $247.50 |
| 100 | $19.95 | $1,995.00 |
| 500 | $16.4 | $8,200.00 |
| 1,000 | $13.95 | $13,950.00 |
EP910DC-40 개요
An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device that fuses the architectural simplicity of PAL-type logic with the re-programmability of UV-erasable EPROM cells. Within the broader taxonomy, EPLDs sit between simple SPLDs (such as PALs and GALs) and modern FPGAs, offering deterministic combinational and registered logic, predictable timing, and erasable programmability at the cost of lower density than an FPGA. The EP910 family belongs to the Classic EPLD category introduced by Altera in the 1980s and remains in service today for legacy industrial and military refresh designs.
Key features of the EP910DC-40 include a maximum propagation delay of 40 ns (commercially graded; the -40 suffix indicates 40 ns tPD), an internal global interconnect that links all 24 macrocells through a single unified bus, up to 240 product terms distributed across the array, two dedicated global clock inputs for synchronous sequential logic, and on-board logic test circuitry enabling AC specification verification during standard production flow. The part is built on a CMOS process that consumes modest power compared with bipolar PAL alternatives of the same era.
Architecturally, the EP910DC-40 uses a PAL-type AND/OR structure in each macrocell. Combinational logic is implemented via AND-plane product terms feeding an OR gate that drives the macrocell output, while registered operation is achieved by routing the OR-plane result through a configurable D flip-flop clocked from one of the two global clock inputs. The 24 I/O pins share connections to both the input array and the macrocell feedback network, allowing pin and feedback resource pooling that maximizes logic utilization per device.
Typical applications include legacy glue logic replacement (replacing multiple 24-pin PALs with a single EPLD), bus-interface adaptation (synchronizing 8-bit and 16-bit buses with predictable timing), address decoding for microprocessor and microcontroller systems, industrial control boards that require ceramic-DIP through-hole packages for harsh environments, and military/aerospace refresh programs where the ceramic DIP form factor and Altera Classic EPLD pinout are mandated.
Designers should note that the DIP-40 ceramic package has long lead times and a shrinking authorized-distribution channel. Most surviving stock is broker or aftermarket; for new designs engineers typically migrate to Altera MAX II CPLDs or modern Lattice ispMACH CPLDs that provide denser, in-system-programmable, and RoHS-compliant equivalents with similar 5V tolerant I/O characteristics.
This page synthesizes distributor pricing, drop-in Classic EPLD alternatives, and practical design notes that are not collated in the original Altera datasheet.
드롭인 대체품: EP910DC-40 — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: EP910DC-40 (동일 폼 팩터 및 풋프린트) — 차이점: Package, Family, Operating Temperature, Supply Voltage (VCC), Architecture.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
EP910DC-35
✅ 드롭인✓ 재고 있음
$10.95 / 개
데이터시트 보기 →EP910DC-30
✅ 드롭인✓ 재고 있음
$15.6 / 개
데이터시트 보기 →EP910DC-15
✅ 드롭인 ⚠️ 사양 미검증✓ 재고 있음
$10.75 / 개
데이터시트 보기 →EP910DC-40 최대 정격 & 전기적 특성
| Device Family | Classic EPLD (EP910 series) |
| Architecture | PAL-type AND/OR, UV-erasable CMOS |
| Macrocells | 24 |
| Dedicated Inputs | 12 |
| Bidirectional I/O Pins | 24 |
| Total Inputs to Logic Array | 36 |
| Product Terms | 240 maximum |
| Maximum Propagation Delay (tPD) | 40 ns |
| Maximum Operating Frequency (fMAX) | 25 MHz |
| Global Clocks | 2 |
| 공급 전압 | 5 V (typical for Classic EPLD family) |
| Operating Temperature (Commercial) | 0 °C to 70 °C |
| 패키지 | DIP-40 (ceramic, through-hole) |
| 실장 유형 | Through-Hole |
| Programming Method | UV-erase + EPROM programmer; on-board logic test circuitry |
EP910DC-40 dip-40 (ceramic, through-hole) 핀 구성 가이드
EP910DC-40(dip-40 (ceramic, through-hole) 패키지)의 핀 구성입니다. 이 디지털 IC에는 GPIO, 통신 인터페이스(UART, SPI, I2C), 전원 핀이 포함되어 있습니다. 대체 핀 기능과 구성 옵션은 제조사 데이터시트를 참조하십시오. 임베디드 시스템 설계와 PCB 레이아웃에 필수적입니다.
다음에 대한 상세 핀아웃 데이터 없음: EP910DC-40.
다음을 참조하십시오: 데이터시트 전체 핀 구성은 다음을 참조하십시오.
일반적인 애플리케이션
EP910DC-40 적합 용도: 7 애플리케이션s: Legacy Glue Logic Replacement, Microprocessor Bus Address Decoding, Industrial Control Board Refresh, Military and Aerospace Avionics Refresh, Bus Interface Adapter (8/16-bit Synchronization), State Machine and Sequential Control Logic, Educational and Engineering Lab Reference Design.
Legacy Glue Logic Replacement
The EP910DC-40's 24 macrocells and 240 product terms let it consolidate multiple 24-pin PALs onto a single ceramic DIP-40 footprint, simplifying legacy glue logic in industrial controllers and telecom backplanes. Designers typically map multiple discrete PAL equations into one device using Altera MAX+PLUS II, then program the chip with a UV-erasable programmer. The 40 ns tPD suits 8 MHz and 10 MHz bus systems; for higher clock rates, drop in the EP910DC-35 instead. Pin-compatible with Altera Classic EPLD family, it preserves the existing 40-pin DIP through-hole assembly flow.
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Microprocessor Bus Address Decoding
The EP910DC-40's 12 dedicated inputs plus 24 bidirectional I/O pins yield 36 logic-array inputs - enough for full 24-bit address decoding plus chip-select generation in 68000, 8086, and Z80 systems. The deterministic 40 ns propagation delay ensures clean CS-to-data timing on asynchronous bus cycles, while two global clock inputs support synchronous wait-state logic. Engineers commonly pair the EP910DC-40 with a peripheral PAL on the same board, then migrate both into one device to free board space. The DIP-40 ceramic package suits through-hole assembly required by many long-lifecycle industrial designs.
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Industrial Control Board Refresh
Factories running 1980s and 1990s PLCs, motor drives, and process controllers still rely on Altera Classic EPLDs because redesigns require costly re-qualification. The EP910DC-40's ceramic DIP-40 package tolerates the conformal coating, vibration, and -40 °C to +85 °C (industrial-version variant) thermal stress typical of these environments. The 5V-tolerant CMOS I/O interfaces directly to legacy TTL bus transceivers without level shifting. For boards that need temperature hardening, the EP910DI-45 (industrial 45 ns variant) is drop-in compatible.
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Military and Aerospace Avionics Refresh
Military and aerospace programs that qualified the Altera Classic EPLD family decades ago continue to source the EP910DC-40 for sustaining engineering on legacy avionics and ground systems. The ceramic DIP-40 package survives the thermal cycling, vibration, and outgassing requirements of DO-160 and MIL-STD-810 environments, while the UV-erasable architecture supports secure re-programming in field depots. Verified parts are typically sourced through QPL/QML channels; for new military designs, Altera recommends migrating to the radiation-tolerant RTAX family, but the EP910DC-40 remains in service for legacy sustainment.
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Bus Interface Adapter (8/16-bit Synchronization)
The EP910DC-40 bridges mismatched 8-bit and 16-bit buses by combining registered and combinational macrocells in one device. Two global clock inputs allow synchronous handshake generation, while the bidirectional I/O pins double as bus transceivers with controlled direction logic. A typical implementation pairs an 8-bit microcontroller peripheral port with a 16-bit ISA bus, achieving full timing closure with the deterministic 40 ns propagation delay. The DIP-40 ceramic package also supports conformal-coated boards used in automotive and industrial test fixtures.
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State Machine and Sequential Control Logic
Each EP910DC-40 macrocell contains a D flip-flop clocked from one of two global clock inputs, so the device efficiently implements Moore and Mealy state machines for sequencing pumps, valves, and relays in process control. The 240 product terms distribute across the 24 macrocells, providing roughly 10 product terms per state - ample for typical 8- to 16-state machines used in industrial automation. Designers report clean timing closure at 25 MHz, with state-transition propagation delays well below the 40 ns maximum. This is a textbook use case for the Classic EPLD.
추천
Educational and Engineering Lab Reference Design
University digital-design labs and engineering training kits still use the EP910DC-40 because its PAL-type AND/OR structure is pedagogically clear and the MAX+PLUS II development environment is well documented. Students can program small state machines, address decoders, and bus arbiters on the bench without learning a vendor-proprietary HDL. The ceramic DIP-40 package is robust to repeated insertion in breadboards and ZIF sockets. The same Altera toolchain still supports modern MAX devices, making the EP910 a useful bridge to contemporary CPLD development.
추천
추천 제품 요약
엔지니어링 참조 데이터: EP910DC-40 — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | EP910DC-35 | EP910DC-30 | EP910DI-45 |
|---|---|---|---|---|
| Brand | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) |
| Package | DIP-40 (ceramic) | DIP-40 (ceramic) - same | DIP-40 (ceramic) - same | DIP-40 (ceramic) - same |
| Macrocells | 24 | 24 | 24 | 24 |
| Total Logic-Array Inputs | 36 | 36 | 36 | 36 |
| Propagation Delay (tPD) | 40 ns | 35 ns | 30 ns | 45 ns |
| Maximum Frequency | 25 MHz | 28.5 MHz | 33 MHz | 22 MHz |
| Operating Temperature | 0 °C to 70 °C (commercial) | 0 °C to 70 °C (commercial) | 0 °C to 70 °C (commercial) | -40 °C to +85 °C (industrial) |
| Global Clocks | 2 | 2 | 2 | 2 |
주요 차별점
- Fastest commercial-grade ceramic DIP-40 Classic EPLD (vs EP910DC-35 / EP910DC-30)
- Drop-in compatibility with industrial-grade variant (vs EP910DI-45)
- Native 5V tolerance without level shifters (vs MAX II EPM240 / ispMACH 4000ZE)
설계 노트
Estimated power calculation: the EP910DC-40 draws approximately 150-300 mA at 5V in CMOS Classic EPLD operation, depending on toggle rate. Confirm Icc on your lot before designing 5V supply headroom; legacy ceramic-DIP lots may exceed the datasheet Icc typical if not properly erased. UV-erase the part for 15-20 minutes under a 12,000 µW/cm² lamp before re-programming, otherwise bit errors may occur. The device is NOT in-system programmable - it requires a separate EPROM programmer and eraser.
Place a 0.1 µF decoupling capacitor within 5 mm of each VCC/ground pin pair on the DIP-40 footprint. The Classic EPLD has multiple power pins that must all be connected, not just one. Add a bulk 10 µF tantalum on the 5V rail near the device. Keep clock traces short and route them over a continuous ground plane to avoid noise-induced false clocking on the two global clock inputs. For bus-interface designs, add 33 ohm series termination on outputs driving >50 mm traces.
Reserve board space for a quartz windowed UV eraser socket if the EP910DC-40 will be re-programmed during development. The ceramic DIP-40 has a quartz lid that allows UV erasure, so do not pot or conformal-coat the top of the part on prototype boards. Reserve a TEST pin connection if you plan to use the on-board logic test circuitry mentioned in the datasheet; this pin allows AC verification during production without a full functional test. For surface-mount retrofits, plan a small adapter PCB to translate the DIP-40 footprint to a TQFP MAX II or ispMACH 4000ZE.
규정 준수 정보
Original Altera Classic EPLDs predate RoHS mandates. Most aftermarket stock RoHS status is unknown; verify with broker documentation. EP910DI-45 (industrial variant) is available for extended-temperature programs but compliance information must be confirmed per lot.
