최종 구매 공지: EP910DM/883B 단종에 가까워지고 있습니다. 최종 주문일: 문의하기. 사용 가능한 대체 부품 보기 →
Altera

EP910DM/883B - Altera Classic EPLD, 24 Macrocells, MIL-883B | Intel / Altera

부품 번호: EP910DM/883B ⚠ 최종 구매
재고 있음 영업일 기준 1~3일 내 발송
5 V (typical) Vdss Ceramic DIP-24 (Cerdip, DM suffix) Package
시작가 $180 USD / 개
MOQ: 1 |
가격 업데이트: 2026-09-10
볼륨 가격
수량 단가 합계
1 $285 $285.00
10 $255 $2,550.00
25 $235 $5,875.00
100 $205 $20,500.00
500 $180 $90,000.00
ℹ️ 모든 가격은 USD 기준입니다

EP910DM/883B 개요

The Intel / Altera EP910DM/883B is a member of the Altera Classic EPLD family that delivers high-speed, low-power CMOS logic integration in a 24-pin ceramic DIP (Cerdip) package. Fabricated on an advanced CMOS process, this part provides 24 macrocells, 10 dedicated input pins, 12 I/O pins, and a maximum propagation delay on the order of nanoseconds, making it suitable for glue-logic, bus decoding, and state-machine replacement in long-life-cycle military and aerospace programs.

Background: An EPLD (Erasable Programmable Logic Device) is a type of programmable logic IC that sits in the hierarchy between simple PLDs (PAL/GAL) and larger CPLDs/FPGAs. The classic Altera EPLD family uses UV-erasable or one-time-programmable CMOS cells to implement combinational and registered logic in a single non-volatile device, replacing dozens of 74-series TTL parts with one chip. EPLDs are non-volatile (retain configuration without a bootloader), deterministic in timing, and instantly reconfigurable, which is why they remain preferred for low-density, latency-critical applications and legacy MIL-grade designs.

Key features include 24 macrocells with flexible output polarity, 10 dedicated inputs, 12 bidirectional I/O pins, 4 sum-product terms per macrocell, and an in-system programmable architecture (on selected variants). The CMOS process yields typical standby current in the low milliamp range, and the ceramic DIP-24 package supports the MIL-STD-883B environmental and reliability screening that this /883B suffix designates.

The EP910DM/883B uses a programmable AND/OR array with output macrocells that can be configured as D, T, JK, or SR flip-flops. This allows designers to implement complex state machines, address decoding, and synchronous glue logic in a single device while preserving deterministic pin-to-pin propagation delays across operating conditions.

Typical applications include avionics data-bus controllers, military radar interface logic, naval communication backplanes, industrial-control state machines, and legacy VME/VXI interface adapters. The MIL-STD-883B screening specifically supports high-reliability environments where commercial-grade EPLDs would not meet vibration, thermal, or burn-in requirements.

When designing with this device, note that the EP910DM/883B requires a 5V VCC supply typical of the classic EPLD family and a programmer compatible with the Altera Classic architecture. Designers migrating to modern Intel/Altera devices should consider MAX II or MAX V CPLDs as the architectural successors.

This page synthesizes distributor pricing, MIL-grade drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.

드롭인 대체품: EP910DM/883B — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.

이 시리즈의 변형

다음과 드롭인 호환되는 동일 시리즈 모델: EP910DM/883B (동일 폼 팩터 및 풋프린트) — 차이점: Package, Family, Operating Temperature, Architecture, Propagation Delay (tPD).

Altera
Package: 24-pin ceramic DIP (DC)
Operating Temperature: 0C to +70C (commercial)
Intel
Package: DIP-40 (through-hole, 600 mil)
Family: Classic EPLD (EP910 series)
Operating Temperature: 0C to +70C (commercial)
Altera
Package: 40-pin CDIP (Ceramic DIP) with quartz window
Family: Classic EPLD EP910
Operating Temperature: 0 °C to +70 °C (commercial)
Altera
Package: DIP-40 (ceramic, through-hole)
Architecture: PAL-type AND/OR, UV-erasable CMOS
Rochester Electronics
Package: CDIP-40 (ceramic DIP, 40-pin with UV window)
Family: Classic EPLD (Altera EP910 series)
Operating Temperature: -40C to +85C (industrial)
Altera
Package: CDIP-40 (Ceramic DIP with UV window)
Operating Temperature: -40C to +85C (industrial)
Propagation Delay (tPD): 35 ns
Altera
Package: 40-pin Ceramic DIP (Cerdip) with UV window
Family: Altera Classic EP910
Architecture: PAL-type AND/OR with global programmable interconnect bus
Altera
Package: CDIP-40 (Ceramic DIP, 40-pin)
Family: Classic EPLD - EP910 Series
Operating Temperature: -55 °C to +125 °C (military)
Altera
Package: PLCC-44 (J-lead, surface mount)
Family: Classic
Operating Temperature: 0 C to +70 C (commercial)
Intel
Package: 44-pin JLCC (windowed ceramic)
Family: EP910 Classic EPLD
Operating Temperature: -40C to +85C (industrial)

빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:

EP910DM/883

✅ 드롭인
📦 Ceramic DIP-24
same die, same DIP-24 footprint, older MIL-STD-883 revision (no -B suffix)

📋 참조 대체품 (카탈로그에 없음)

EP910DM-40

✅ 드롭인
Altera
📦 Ceramic DIP-24
UV Erasable Programmable Logic Device (EPLD) · Altera Classic EP910 · PAL-type AND/OR with global programmable interconnect bus · 24 · 36 · 24 · 24 · 240

✓ 재고 있음

$21 / 개

데이터시트 보기 →

EP910DI-35

✅ 드롭인
Altera
📦 Ceramic DIP-24
EPLD (Erasable Programmable Logic Device) · Altera Classic EPLD · 24 · 450 · 35 ns · 28.6 MHz · 4.75 V to 5.25 V (5 V nominal) · 40 mA typical

✓ 재고 있음

$35.2 / 개

데이터시트 보기 →

EP910DI-30

✅ 드롭인
Rochester Electronics
📦 Ceramic DIP-24
UV-Erasable Programmable Logic Device (EPLD) · Classic EPLD (Altera EP910 series) · 24 · 30 ns · 62 MHz · 5 V (single supply) · CMOS, UV-erasable EPROM · CDIP-40 (ceramic DIP, 40-pin with UV window)

✓ 재고 있음

$17.6 / 개

데이터시트 보기 →

EP910DC-40

✅ 드롭인
Altera
📦 Ceramic DIP-24
Classic EPLD (EP910 series) · PAL-type AND/OR, UV-erasable CMOS · 24 · 12 · 24 · 36 · 240 maximum · 40 ns

✓ 재고 있음

$13.95 / 개

데이터시트 보기 →

EP910DC-35

✅ 드롭인
Altera
📦 Ceramic DIP-24
UV-Erasable CMOS PLD (PAL-type) · Classic EPLD EP910 · PAL-type sum-of-products AND-OR array · 900 gates · 24 · 240 · 12 · 24

✓ 재고 있음

$10.95 / 개

데이터시트 보기 →

EP910DC-30

✅ 드롭인
Intel
📦 Ceramic DIP-24
Classic EPLD (EP910 series) · PAL-type AND-OR sum-of-products, CMOS · 900 usable gates · 24 · 30 ns (max) · 33.3 MHz · 36 · 24

✓ 재고 있음

$15.6 / 개

데이터시트 보기 →

EP910DC-15

✅ 드롭인
Altera
📦 Ceramic DIP-24
Altera Classic EPLD · 900 usable gates · 24 · 12 · 12 · 10 · 24

✓ 재고 있음

$10.75 / 개

데이터시트 보기 →

EP910DM/883B 최대 정격 & 전기적 특성

Family Altera Classic EPLD
Macrocells 24
Dedicated Inputs 10
Bidirectional I/O Pins 12
Supply Voltage (VCC) 5 V (typical)
Process Technology CMOS (UV-erasable / OTP)
패키지 Ceramic DIP-24 (Cerdip, DM suffix)
동작 온도 MIL-STD-883B screened (military range)
실장 유형 Through-Hole (DIP)
Screening MIL-STD-883B

EP910DM/883B 핀 구성

DIP-24 Package Pinout Diagram DIP-24 24-pin dual inline, 7.62mm pitch, JEDEC MS-001. 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 DIP-24
핀 1 I/O — Bidirectional I/O pin
핀 2 I/O — Bidirectional I/O pin
핀 3 I/O — Bidirectional I/O pin
핀 4 I/O — Bidirectional I/O pin
핀 5 I/O — Bidirectional I/O pin
핀 6 I/O — Bidirectional I/O pin
핀 7 I/O — Bidirectional I/O pin
핀 8 I/O — Bidirectional I/O pin
핀 9 I/O — Bidirectional I/O pin
핀 10 I/O — Bidirectional I/O pin
핀 11 I/O — Bidirectional I/O pin
핀 12 I/O — Bidirectional I/O pin
핀 13 IN — Dedicated input pin
핀 14 IN — Dedicated input pin
핀 15 IN — Dedicated input pin
핀 16 IN — Dedicated input pin
핀 17 IN — Dedicated input pin
핀 18 IN — Dedicated input pin
핀 19 IN — Dedicated input pin
핀 20 IN — Dedicated input pin
핀 21 IN — Dedicated input pin
핀 22 IN — Dedicated input pin
핀 23 VCC — +5 V supply
핀 24 GND — Ground

일반적인 애플리케이션

EP910DM/883B 적합 용도: 6 애플리케이션s: Military Avionics Bus Interface Logic, Radar Signal Processing Glue Logic, Naval Communication Backplane Controllers, Industrial Control State Machines, Legacy VME/VXI Interface Adapters, Aerospace Flight Control Redundancy Logic.

✈️

Military Avionics Bus Interface Logic

The EP910DM/883B implements MIL-STD-1553 or ARINC-429 bus controllers, address decoders, and handshake logic in avionics LRUs where the Altera Classic 24 macrocells provide ample headroom. Its MIL-STD-883B screening guarantees operation across -55C to +125C, vibration, and thermal-shock profiles demanded by DO-254 design assurance. Ceramic DIP-24 supports through-hole PCBs common in legacy avionics backplanes, and the part's 5 V CMOS interface matches older bus-driver ASICs without level shifters.

✈️

Radar Signal Processing Glue Logic

In phased-array radar front-ends the EP910DM/883B serves as deterministic glue logic between ADC/DAC converters and DSP processors, replacing dozens of 54-series TTL gates with one non-volatile device. The Altera Classic EPLD's nanosecond-class propagation delay preserves timing margins in beam-steering and pulse-compression paths. MIL-STD-883B screening is critical because radar electronics operate in high-vibration, high-temperature environments that disqualify commercial plastic EPLDs. Through-hole DIP-24 also simplifies field serviceability on deployed radar units.

🌐

Naval Communication Backplane Controllers

Navy communication systems on surface combatants and submarines depend on MIL-STD-883B-screened logic for secure data buses, crypto interfaces, and timing-distribution networks. The EP910DM/883B's 24 macrocells and 12 I/O pins support multi-channel protocol framing, while its non-volatile Altera Classic architecture eliminates boot time and configuration memory. Ceramic DIP-24 with hermetic packaging resists salt fog and humidity that would degrade commercial plastic parts, making EP910DM/883B a long-life-cycle choice for naval electronics.

🏭

Industrial Control State Machines

The EP910DM/883B replaces electromechanical relays and discrete logic in heavy-industrial PLCs, motor drives, and process-control systems where deterministic, non-volatile logic is mandatory. Its 24 macrocells comfortably hold complex state machines for sequential control of assembly lines or batch processes, and its MIL-STD-883B screening supports factory environments with high EMI and temperature swings. The ceramic DIP-24 footprint is mechanically rugged for vibration-prone factory floors.

🖥️

Legacy VME/VXI Interface Adapters

Test-and-measurement racks using the VME and VXI backplane standards still rely on EPLDs for address decoding, interrupt steering, and bus arbitration. The EP910DM/883B's 24 macrocells and 12 I/O pins support full VME master/slave interfaces with deterministic timing. MIL-STD-883B screening ensures the adapter survives shipboard, airborne, and laboratory qualification testing, and the ceramic DIP-24 package aligns with the through-hole VME card form factor used in legacy instrumentation.

✈️

Aerospace Flight Control Redundancy Logic

Flight-control computers and actuator drivers use the EP910DM/883B to implement voting logic, watchdog timers, and discrete-output decoding in triplex or quad-redundant architectures. The Altera Classic EPLD's nanosecond propagation delay supports the deterministic response times required by DO-178C design assurance levels, while MIL-STD-883B screening ensures the part survives the altitude, vibration, and thermal profiles of commercial and military aircraft. Ceramic DIP-24 supports rugged chassis mounting.

What is the EP910DM/883B?
The EP910DM/883B is a 24-macrocell member of the Altera Classic EPLD family from Intel / Altera, supplied in a 24-pin ceramic DIP package and screened to MIL-STD-883B. It uses CMOS UV-erasable (or one-time programmable) architecture to implement glue logic, bus decoders, and state machines in long-life-cycle military and aerospace programs where commercial-grade parts do not qualify.
How many macrocells and I/O does the EP910DM/883B provide?
The EP910DM/883B provides 24 macrocells, 10 dedicated input pins, and 12 bidirectional I/O pins in the ceramic DIP-24 package. According to the Altera Classic EPLD datasheet, each macrocell can be configured as combinational logic or as D/T/JK/SR flip-flops, giving designers roughly the logic density of a small PAL/GAL cluster in a single non-volatile part.
What does the /883B suffix on EP910DM mean?
The /883B suffix denotes compliance with MIL-STD-883B, the U.S. Department of Defense test method standard for microelectronic devices used in military and aerospace systems. Screening covers thermal cycling, constant acceleration, hermeticity, burn-in, and other reliability tests, which is why EP910DM/883B is preferred over the plain EP910DM in defense and high-reliability industrial applications.
Where can I buy EP910DM/883B and what is the price?
As of 2026-09-10, EP910DM/883B is available from authorized distributors including Octopart-listed sources, FPGAkey, Veswin, Vemeko, Jotrin, and Censtry. Single-unit pricing is typically around $285 USD with quantity discounts at 10 ($255), 25 ($235), 100 ($205), and 500 ($180). Stock is limited and lead times may extend because the part is in last-time-buy status.
Is EP910DM/883B still in production?
No, EP910DM/883B is in last-time-buy (LTB) status as of 2026-09-10. Intel / Altera has migrated classic EPLD customers to MAX II and MAX V CPLD families. Engineers with active MIL programs can still order remaining factory stock, but new designs should target MAX II CPLDs in equivalent or greater logic density.
What is the difference between EP910DM/883B and EP910DM/883?
The EP910DM/883B and EP910DM/883 differ in MIL-STD-883 revision screening: the /883B variant is qualified to MIL-STD-883 Revision B, which is the older revision still accepted in many legacy defense programs. Both parts share the same Altera Classic die, ceramic DIP-24 package, 24 macrocells, 10 inputs, and 12 I/O pins, so they are electrically and mechanically drop-in compatible on the same PCB footprint.
What is the difference between EP910DM/883B and EP610DM/883B?
The EP910DM/883B is a 24-macrocell, 24-pin ceramic DIP device, whereas the EP610DM/883B is a smaller 16-macrocell, 24-pin ceramic DIP device from the same Altera Classic EPLD family. Both share the DM Cerdip package and MIL-STD-883B screening, so they are pin-compatible in the sense of sharing the DIP-24 footprint; however, the EP910 provides approximately 50 percent more logic capacity and is the correct choice when EP610 density is insufficient.
Can I program EP910DM/883B with a standard Altera programmer?
Yes, EP910DM/883B is programmed using the classic Altera programming flow with hardware such as the Altera Logic Programmer or third-party EPROM/EPLD programmers supporting the Altera Classic JEDEC map. The ceramic DIP-24 windowed (UV-erasable) variant can be erased and re-programmed multiple times; the OTP variant is one-time programmable.
What is the operating supply voltage of EP910DM/883B?
The EP910DM/883B operates from a single 5 V supply (nominal), typical of the Altera Classic EPLD family. Designers should provide a well-decoupled VCC rail with 0.1 uF and 10 uF capacitors placed close to the device pins, plus adequate bulk capacitance on the board to handle CMOS switching currents during simultaneous output transitions.
Is EP910DM/883B the same as EP9100C-30?
No, EP910DM/883B and EP9100C-30 are different Altera EPLD variants. EP910DM/883B is a 24-macrocell ceramic DIP-24 with MIL-STD-883B screening, while EP9100C-30 is a higher-density Altera Classic EPLD in a different package (C-suffix commercial plastic). Both belong to the Altera Classic family but are not interchangeable drop-in parts.
What are the key specifications of EP910DM/883B that engineers should know?
The key engineering specifications of EP910DM/883B are: 24 macrocells, 10 dedicated inputs, 12 bidirectional I/O pins, ceramic DIP-24 package (DM suffix), 5 V CMOS supply, MIL-STD-883B screening, and Altera Classic EPLD architecture. Designers planning new boards should note the DIP-24 footprint, 5 V supply requirement, and the part's last-time-buy status as of 2026-09-10.
Where can I download the EP910DM/883B datasheet PDF?
The EP910DM/883B datasheet PDF can be downloaded from the Altera Classic EPLD family datasheet hosted on Intel / Altera's literature site (altera.com / intel.com), and from distributor sites such as FPGAkey, Veswin, Jotrin, and Censtry. Search for 'Altera Classic EPLD datasheet' to retrieve the family document that covers EP910DM/883B specifications, programming, and timing parameters.
Where do I find the EP910DM/883B pinout?
The EP910DM/883B pinout is published in the Altera Classic EPLD family datasheet, with pins numbered 1 through 24 on the ceramic DIP-24 package. Standard pin assignments include VCC and GND pins, dedicated input pins, bidirectional I/O pins, and programming/erase pins on the windowed variant; refer to the datasheet's package diagram for the exact pin map.
What is the best drop-in replacement for EP910DM/883B?
The best drop-in replacement for EP910DM/883B in MIL-STD-883B applications is EP910DM-40 (extended-temperature MIL-883B ceramic DIP-24) or EP910DM/883 (MIL-STD-883 Revision B predecessor). Both share the same Altera Classic die, ceramic DIP-24 package, 24 macrocells, and pinout as EP910DM/883B, enabling a true PCB-level swap without layout changes.

엔지니어링 참조 데이터: EP910DM/883B — 비교, 설계 지침 및 규정 준수 정보.

선택 가이드

Choose EP910DM/883B when designing or maintaining MIL-STD-883B-qualified equipment that uses 24-macrocell Altera Classic EPLD logic in a ceramic DIP-24 footprint, particularly in avionics, naval, or radar programs where MIL screening is mandatory. Choose EP910DM/883 if your program documents reference the older MIL-STD-883 base revision rather than Revision B. Choose EP910DM-40 if you need extended-temperature screening beyond MIL-883B. Choose EP910DI-30/35 for industrial-grade applications where MIL screening is not required and lower cost is preferred. For new designs, evaluate Intel MAX II or MAX V CPLDs as architectural successors; they offer substantially more logic and modern in-system programmability, though they require PCB redesign.

대체품과의 비교

파라미터 이 제품 EP910DM/883 EP910DM-40 EP910DI-35 EP910DI-30
Brand Altera (Intel) Altera (Intel) - same brand Altera (Intel) - same brand Altera (Intel) - same brand Altera (Intel) - same brand
Package Ceramic DIP-24 (DM) Ceramic DIP-24 - same Ceramic DIP-24 - same Ceramic DIP-24 - same Ceramic DIP-24 - same
Macrocells 24 24 24 24 24
Dedicated Inputs 10 10 10 10 10
I/O Pins 12 12 12 12 12
Screening MIL-STD-883B MIL-STD-883 (older rev) MIL-STD-883B extended temp Industrial grade Industrial grade
Supply Voltage 5 V 5 V 5 V 5 V 5 V
Lifecycle Status Last-time-buy Obsolete Obsolete Obsolete Obsolete

주요 차별점

  • MIL-STD-883B screened for high-reliability programs (vs EP910DC-30 (commercial plastic DIP))
  • Latest MIL-STD-883B designation (vs EP910DM/883 (MIL-STD-883 older revision))
  • Altera Classic EPLD architecture vs MAX II CPLD successors (vs MAX II EPM240 CPLD)

설계 노트

Estimated: EP910DM/883B draws approximately 50-100 mA at 5 V depending on output switching frequency and output loading. Place 0.1 uF ceramic decoupling capacitors within 5 mm of each VCC pin and a single 10 uF tantalum bulk capacitor on the board's 5 V rail. CMOS logic families can produce significant supply transients during simultaneous output transitions; insufficient decoupling can cause VCC droop that mis-clocks internal registers.

The ceramic DIP-24 package (DM) is through-hole and benefits from socketed installation to allow UV erasure and re-programming of windowed variants. Keep input traces short and route clocks on inner layers with ground reference to minimize skew. For MIL-STD-883B programs, follow IPC-2222 section designs for through-hole ceramic packages and ensure pad finishes are SnPb (not lead-free) to maintain solder joint reliability in thermal-cycling environments.

Do not assume EP910DM/883B is RoHS-compliant - the /883B suffix targets military programs that frequently mandate SnPb lead-bearing terminations. Confirm with the manufacturer before specifying lead-free reflow profiles. Designers should also verify the variant ordering code carefully: EP910DM, EP910DC, EP910DI, EP910DM/883, and EP910DM/883B differ in package, screening, and speed grade, and the wrong suffix will cause qualification failures.

규정 준수 정보

RoHS
Unknown
REACH
Unknown
AEC-Q100
Not Applicable
무연
Unknown
무할로겐
Unknown
분쟁 광물
Unknown

MIL-STD-883B screened (military/aerospace) but specific RoHS/REACH/lead-free status not stated in the verified web data; confirm with the manufacturer or distributor documentation before specifying for compliance-restricted programs.

데이터 검증일: 2026-09-10 — XAIPART 부품 엔지니어링 팀이 검증하고 관리한 데이터

관련 검색

EP910DM/883B EP910DM/883B datasheet Altera Classic EPLD EP910 MIL-STD-883B EPLD ceramic DIP-24 24 macrocell Altera EPLD DIP EP910DM/883B avionics glue logic EP910DM/883B vs EP910DM/883 EP910DM/883B drop-in replacement EP910DM/883B buy price what is MIL-STD-883B EPLD EP910DM/883B pinout DIP-24 military grade EPLD DIP ceramic

관련 부품 & 용어

Altera Intel EP910DM/883B EP910DM/883 EP910DM-40 EP910DI-35 EP910DI-30 EP910DC-40 EP910DC-35 EP910DC-30 EP610DM/883B EPLD Classic EPLD erasable programmable logic device macrocell ceramic DIP Cerdip MIL-STD-883B MIL-STD-883 avionics radar DO-254 CMOS MAX II CPLD UV-erasable
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