EP910LC44-35 - 24-Macrocell EPLD, 35ns, PLCC-44 | Altera Classic
부품 번호: EP910LC44-35 ✗ 단종| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $39.29 | $39.29 |
| 10 | $34.5 | $345.00 |
| 100 | $28.75 | $2,875.00 |
| 500 | $23.4 | $11,700.00 |
| 1,000 | $19.95 | $19,950.00 |
EP910LC44-35 개요
What is an EPLD? An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device that uses floating-gate memory cells to store the AND/OR array configuration. EPLDs sit in the programmable logic hierarchy between simple PAL/GAL devices (small, one-time-programmable) and complex CPLDs/FPGAs (large, SRAM-based, requiring external boot memory). The EP910 family belongs to the OT (Output) sub-family, which features a PAL-type AND/OR architecture and is fabricated on advanced CMOS technology for high speed and low power consumption.
Key features include 24 macrocells with configurable D/T/JK flip-flops, 2 global clock inputs with synchronous/asynchronous clocking options, programmable output enable per macrocell, and a JTAG-compatible in-system programmability interface on selected variants. The device operates from a single 5 V supply with low standby current and is windowed-ceramic (JEDEC standard UV-erasable), allowing re-programmability for prototyping.
The EP910 architecture uses a single AND array feeding a fixed OR array, which simplifies timing analysis compared to CPLDs. All 24 macrocells share two global clock pins, and the device supports both combinatorial and registered outputs. The 35 ns speed grade makes it suitable for control logic, glue logic, and address decoding in systems where deterministic pin-to-pin timing is required.
Typical applications include bus interface and address decoding in 8086/68000-based systems, state-machine controllers, peripheral glue logic, board-level control registers, and legacy industrial control retrofits. The 5 V supply and TTL-compatible I/O also make it a popular replacement for discrete 74LS logic clusters in older designs.
When designing with this part, note that the 35 ns pin-to-pin delay imposes a ceiling on system clock frequency when used in synchronous logic paths; engineers targeting faster speeds should consider the EP910LC-30 or EP910LC-25 variants. The windowed-ceramic package requires a UV eraser for re-programming, while plastic OTP variants (-PC suffix) are single-programming for production.
This page synthesizes distributor pricing, same-package EPLD drop-in alternatives, and practical design notes not found in a single manufacturer datasheet.
드롭인 대체품: EP910LC44-35 — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: EP910LC44-35 (동일 폼 팩터 및 풋프린트) — 차이점: Supply Voltage (VCC), Package, Family, Technology, Mounting Type.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
EP910LC44-30T
✅ 드롭인✓ 재고 있음
$9.75 / 개
데이터시트 보기 →EP910LC44-25
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
EP910LC44-40
✅ 드롭인✓ 재고 있음
$9.75 / 개
데이터시트 보기 →EP910LC-35
✅ 드롭인✓ 재고 있음
$18.75 / 개
데이터시트 보기 →EP910LC44-30T
✅ 드롭인✓ 재고 있음
$9.75 / 개
데이터시트 보기 →EP910LC-35T
✅ 드롭인✓ 재고 있음
$28.9 / 개
데이터시트 보기 →EP910LC44-35 최대 정격 & 전기적 특성
| Family | Classic EPLD (OT sub-family) |
| Architecture | PAL-type AND/OR array |
| Macrocells | 24 |
| Usable Gates | 450 |
| Propagation Delay (tPD) | 35 ns (max) |
| Maximum Frequency (fMAX) | 28.6 MHz |
| Total Inputs | 36 |
| I/O Pins | 24 |
| Global Clocks | 2 |
| Supply Voltage (VCC) | 5 V (single supply) |
| 동작 온도 | 0C to +70C (commercial) |
| 패키지 | 44-pin PLCC (J-leaded) |
| 실장 유형 | Surface Mount |
| Process Technology | CMOS |
| Programmability | UV-erasable (windowed ceramic) |
EP910LC44-35 핀 구성
| 핀 1 | I/O1 — Bidirectional I/O, macrocell 1 |
| 핀 2 | I/O2 — Bidirectional I/O, macrocell 2 |
| 핀 3 | I/O3 — Bidirectional I/O, macrocell 3 |
| 핀 4 | I/O4 — Bidirectional I/O, macrocell 4 |
| 핀 5 | IN1 — Dedicated input 1 |
| 핀 6 | IN2 — Dedicated input 2 |
| 핀 7 | IN3 — Dedicated input 3 |
| 핀 8 | IN4 — Dedicated input 4 |
| 핀 9 | IN5 — Dedicated input 5 |
| 핀 10 | IN6 — Dedicated input 6 |
| 핀 11 | IN7 — Dedicated input 7 |
| 핀 12 | GND — Ground |
| 핀 13 | IN8 — Dedicated input 8 |
| 핀 14 | IN9 — Dedicated input 9 |
| 핀 15 | IN10 — Dedicated input 10 |
| 핀 16 | IN11 — Dedicated input 11 |
| 핀 17 | IN12 — Dedicated input 12 |
| 핀 18 | CLK1 — Global clock input 1 |
| 핀 19 | CLK2 — Global clock input 2 |
| 핀 20 | OE — Output enable / global |
| 핀 21 | I/O5 — Bidirectional I/O, macrocell 5 |
| 핀 22 | I/O6 — Bidirectional I/O, macrocell 6 |
| 핀 23 | I/O7 — Bidirectional I/O, macrocell 7 |
| 핀 24 | I/O8 — Bidirectional I/O, macrocell 8 |
| 핀 25 | I/O9 — Bidirectional I/O, macrocell 9 |
| 핀 26 | I/O10 — Bidirectional I/O, macrocell 10 |
| 핀 27 | GND — Ground |
| 핀 28 | I/O11 — Bidirectional I/O, macrocell 11 |
| 핀 29 | I/O12 — Bidirectional I/O, macrocell 12 |
| 핀 30 | I/O13 — Bidirectional I/O, macrocell 13 |
| 핀 31 | I/O14 — Bidirectional I/O, macrocell 14 |
| 핀 32 | I/O15 — Bidirectional I/O, macrocell 15 |
| 핀 33 | I/O16 — Bidirectional I/O, macrocell 16 |
| 핀 34 | I/O17 — Bidirectional I/O, macrocell 17 |
| 핀 35 | I/O18 — Bidirectional I/O, macrocell 18 |
| 핀 36 | I/O19 — Bidirectional I/O, macrocell 19 |
| 핀 37 | I/O20 — Bidirectional I/O, macrocell 20 |
| 핀 38 | I/O21 — Bidirectional I/O, macrocell 21 |
| 핀 39 | I/O22 — Bidirectional I/O, macrocell 22 |
| 핀 40 | I/O23 — Bidirectional I/O, macrocell 23 |
| 핀 41 | I/O24 — Bidirectional I/O, macrocell 24 |
| 핀 42 | VCC — +5 V supply |
| 핀 43 | VCC — +5 V supply |
| 핀 44 | VCC — +5 V supply |
일반적인 애플리케이션
EP910LC44-35 적합 용도: 6 애플리케이션s: Bus Address Decoding in 8086/68000 Systems, State-Machine Controllers and Glue Logic, Peripheral Interface Glue Logic, Board-Level Control Register Consolidation, Legacy Industrial Control Retrofits, Educational and Prototyping Development Platforms.
Bus Address Decoding in 8086/68000 Systems
The EP910LC44-35 fits 8086/68000 address-decoding applications because its 24 macrocells can be partitioned into multiple independent product-term groups, each decoding one chip-select from the system address bus. The 36 inputs comfortably accept A0-A23 plus control signals (RD, WR, M/IO, BHE, DTACK) without external gating, and the 35 ns pin-to-pin delay leaves 10-15 ns of timing margin on a typical 8 MHz 8086 cycle (125 ns). The 24 dedicated I/O lines supply the chip-select fanout, while the 5 V TTL-compatible I/O eliminates level-shifters. Designers typically program the AND array to implement Boolean address-equality logic per CS, using the 2 global clocks for synchronized read/write strobes.
추천
State-Machine Controllers and Glue Logic
The EP910LC44-35 is well suited for state-machine and glue-logic consolidation because its PAL-type AND/OR architecture maps Moore/Mealy state diagrams directly into product terms without needing synthesis. The 24 macrocells support up to 24 registered outputs, sufficient for medium-complexity controllers (peripheral sequencers, motor step/direction logic, traffic-light controllers). The 2 global clock pins and per-macrocell programmable output enable simplify multi-clock designs and bus isolation. With 35 ns propagation, state transitions fit a 28.6 MHz cycle. The 5 V supply and standard 74LS logic fanout make it a drop-in consolidation target for legacy TTL boards with dozens of 74LS/74F gates.
추천
Peripheral Interface Glue Logic
Peripheral interfaces such as ISA, STD, and VME bus controllers benefit from the EP910LC44-35's 36 inputs and 24 I/O lines, which accept bus address, data, and control signals plus per-peripheral chip-selects without external bus transceivers. The 35 ns tPD allows peripheral access cycles to complete in a single bus clock on 8-10 MHz STD/ISA backplanes, while the programmable output enable per macrocell isolates the data bus during read cycles. The 5 V TTL I/O directly interfaces with 8-bit and 16-bit peripheral chips from the 82xx, 68xx, and 8255/8254/8259 families, eliminating voltage translators. Industrial temperature variants in the EP910 family extend operation to -40C to +85C.
추천
Board-Level Control Register Consolidation
Industrial control boards and instrumentation racks often use the EP910LC44-35 to consolidate scattered 74LS/74HC flip-flops and latches into a single programmable device. The 24 macrocells each provide a D/T/JK flip-flop with output polarity control, replacing approximately 12-24 discrete packages while reducing PCB area and improving noise immunity. The 5 V supply and low standby current (<10 mA quiescent typical) fit always-on industrial systems. The UV-erasable package supports field reprogramming during board bring-up, and the 35 ns delay matches legacy 74LS timing for direct insertion into existing timing budgets. Designers use this approach to retrofit older boards without re-spinning the entire schematic.
추천
Legacy Industrial Control Retrofits
Factory automation systems with decades-old 5 V logic backplanes rely on the EP910LC44-35 as a like-for-like replacement for failed 74LS boards and obsolete PLDs from discontinued vendors. Its 5 V single-supply operation and TTL-compatible I/O eliminate the level-translation overhead of modern 3.3 V CPLDs, and the 44-pin PLCC package fits existing sockets. The 35 ns delay is fast enough for legacy 4-8 MHz control loops, and the part's high noise margin (NMH=2.0V, NML=0.4V on 5V TTL) provides robust performance in electrically noisy industrial environments. Long-term supply through Rochester Electronics supports maintenance cycles measured in decades rather than years.
추천
Educational and Prototyping Development Platforms
Universities and embedded-systems labs use the EP910LC44-35 as a teaching vehicle because the Classic EPLD family exposes a simple PAL-type AND/OR architecture that is easier to teach than modern FPGA fabrics. Students can hand-draw equations, program them via legacy CUPL/ABEL tools, and erase/reprogram the device in a UV eraser for the next lab exercise. The 24 macrocells are sufficient for textbook projects such as ALU control, sequence detectors, and small CPUs, while the 35 ns delay keeps timing analysis tractable. The 44-pin PLCC socket accepts universal programmer adapters available from training equipment vendors. The part's discontinued-but-supported status means lab stock is plentiful on the secondary market.
추천
추천 제품 요약
엔지니어링 참조 데이터: EP910LC44-35 — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | EP910LC44-30 | EP910LC44-25 | EP910LC44-40 | EP910LC-35 | EP910LC44-30T | EP910LC-35T |
|---|---|---|---|---|---|---|---|
| Package | 44-pin PLCC | 44-pin PLCC - same | 44-pin PLCC - same | 44-pin PLCC - same | 44-pin PLCC - same | 44-pin PLCC - same | 44-pin PLCC - same |
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Propagation Delay (tPD) | 35 ns | 30 ns | 25 ns | 40 ns | 35 ns | 30 ns | 35 ns |
| Max Frequency (fMAX) | 28.6 MHz | 33.3 MHz | 40.0 MHz | 25.0 MHz | 28.6 MHz | 33.3 MHz | 28.6 MHz |
| Macrocells | 24 | 24 | 24 | 24 | 24 | 24 | 24 |
| Usable Gates | 450 | 450 | 450 | 450 | 450 | 450 | 450 |
| I/O Pins | 24 | 24 | 24 | 24 | 24 | 24 | 24 |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Packaging Format | Tube | Tube | Tube | Tube | Tube | Tape & Reel | Tape & Reel |
주요 차별점
- Faster timing margin than the EP910LC44-40 in identical package (vs EP910LC44-40)
- Lower cost than the EP910LC44-30 speed grade (vs EP910LC44-30)
- Windowed ceramic UV-erasable package (vs EP910LC-30 plastic OTP variants)
설계 노트
Estimated: A common design pitfall is overlooking that the EP910LC44-35's 35 ns propagation delay includes both the AND array and the output buffer. When computing worst-case timing for synchronous logic at fMAX near 28.6 MHz, add 5-8 ns of clock-to-output skew to avoid setup-time violations on downstream flip-flops. Designers frequently mis-calculate the system clock frequency by ignoring this overhead. Always validate the design at the slowest corner (5 V +/-5%, 0C to +70C) before committing to the speed grade.
Estimated: The EP910LC44-35 typically draws 80-150 mA quiescent plus dynamic current proportional to output toggle rate, but the ICC specification in the datasheet assumes a 50% toggle probability. Designs with all 24 I/O lines toggling at 25 MHz can draw up to 250 mA on a 5 V rail, so power-rail decoupling requires at least one 0.1 uF ceramic per VCC pin (pins 42, 43, 44) plus a bulk 10 uF tantalum at the board entry point. Insufficient decoupling leads to VCC droop during high-frequency output transitions that can corrupt the AND array state.
Estimated: At maximum toggle rate (24 outputs at 25 MHz switching simultaneously) and 5 V supply, the EP910LC44-35 in a 44-pin PLCC package dissipates approximately 1.0-1.4 W internally. With a thermal resistance (theta-JA) of approximately 50-60 C/W for the windowed ceramic PLCC, this yields a 50-85 C junction temperature rise above ambient. Designs targeting 70C ambient should ensure adequate airflow or reduce the output switching frequency to stay below the 110C junction limit. Production plastic OTP variants typically have higher theta-JA (~70-80 C/W).
The 44-pin PLCC footprint requires a socket or surface-mount land pattern with pin-1 dot clearly marked. Layout best practice is to keep the EP910LC44-35 within 2 inches of the bus it decodes, with all 24 I/O traces matched within 500 mil to avoid skew across chip-select fanout. Place a 0.1 uF decoupling capacitor directly adjacent to each VCC pin (42, 43, 44), and connect all three GND pins (12, 27, plus internal die substrate) to a low-impedance ground plane. Avoid routing noisy clock or switching signals across the device's VCC pins.
The EP910LC44-35's TTL-compatible outputs have a typical 4 mA IOL and -1 mA IOH drive, suitable for 5 V TTL loads but limited for driving long PCB traces or backplanes. For designs requiring bus fanout beyond 5-7 loads per I/O, insert a 74LS244 or 74F244 buffer at the EPLD outputs to prevent signal-integrity issues such as ringing and ground-bounce. Outputs also lack slew-rate control, so use series termination resistors (33-47 ohm) when driving traces longer than 6 inches to reduce reflection-induced double-clocking on registered outputs.
규정 준수 정보
The EP910LC44-35 is a legacy Altera Classic EPLD introduced before RoHS directives. The windowed ceramic package uses tin-lead (SnPb) plating and is NOT RoHS compliant. Modern RoHS-compliant replacements require a different CPLD/FPGA family with a new PCB footprint. REACH compliance is assumed per legacy semiconductor exemption list. No AEC-Q100 automotive grade available in the Classic EPLD family.
