EP910LI-12 - 24-Macrocell Classic EPLD, 12ns PLCC-28 | Altera
부품 번호: EP910LI-12 ✗ 단종| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $25.1 | $251.00 |
| 100 | $21.75 | $2,175.00 |
| 500 | $18.4 | $9,200.00 |
| 1,000 | $15.95 | $15,950.00 |
EP910LI-12 개요
Background: an EPLD (Erasable Programmable Logic Device) is a type of programmable logic IC that sits between simple SPLDs/CPLDs and high-density FPGAs. EPLDs use EPROM, EEPROM, or flash cells to retain configuration, combine AND/OR arrays with output macrocells, and historically delivered fast deterministic propagation delays in the 5-15 ns range. The EP910 belongs to the Classic EPLD family hierarchy: EPLD > programmable logic > PLD > digital IC > semiconductor. Classic EPLDs were widely deployed in the 1990s for glue logic, address decoding, and peripheral interfacing where speed and simplicity outweighed gate count.
Key features of the EP910LI-12 include 24 macrocells, 36 inputs (with input registers), 24 I/O pins, 76.9 MHz maximum operating frequency, and 12 ns worst-case combinatorial propagation delay (tPD). Power consumption is specified at less than 200 mW typical at 5 V, with TTL-compatible I/O and a 5 V VCC supply. Programming uses the original Altera Master Programming Unit (MPU) or compatible third-party programmers via the dedicated program/erase pins, and the ceramic windowed package enables UV erasure for prototyping and design iteration.
Typical applications include 5V bus arbitration, address decoding, peripheral interface glue logic, state machines, and legacy system retrofits. When designing, ensure all inputs are tied to a defined logic level to avoid floating-pin issues, observe the recommended decoupling scheme (one 0.1 uF capacitor per VCC pin), and verify that the chosen programmer supports the Classic EPLD JTAG/byte-blaster protocols before committing to the EP910LI-12. Note that Altera Classic EPLDs are mature EOL components - consult Rochester Electronics for current authorized inventory and lifecycle data.
This page synthesizes distributor pricing, drop-in alternatives from the same Classic EPLD family, and practical design notes not found in the original Altera datasheet.
드롭인 대체품: EP910LI-12 — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: EP910LI-12 (동일 폼 팩터 및 풋프린트) — 차이점: Package, Supply Voltage (VCC), Operating Temperature, Family, Mounting Type.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
EP910LC-12
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
EP910ILI-12
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
EP910IPC-12
✅ 드롭인✓ 재고 있음
$14.2 / 개
데이터시트 보기 →EP910LC44-12
✅ 드롭인 ⚠️ 사양 미검증📋 참조 대체품 (카탈로그에 없음)
EP910LI-35
✅ 드롭인✓ 재고 있음
$25.8 / 개
데이터시트 보기 →EP910LI-12 최대 정격 & 전기적 특성
| Device Family | Altera Classic EPLD |
| Macrocells | 24 |
| Usable Gates | 450 |
| Propagation Delay (tPD) | 12 ns |
| Maximum Frequency (fMAX) | 76.9 MHz |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V typical) |
| I/O Pins | 24 |
| Inputs (with input registers) | 36 |
| 패키지 | 28-PLCC (windowed ceramic, J-Lead) |
| 동작 온도 | -40C to +85C (industrial) |
| Process Technology | 1.0-micron CMOS EPROM |
| Power Dissipation (typical) | 200 mW at 5 V |
| Programming Method | UV-erasable via windowed package |
| Logic Compatibility | TTL-compatible I/O |
| RoHS 상태 | non_compliant (ceramic windowed package) |
EP910LI-12 핀 구성
| 핀 1 | I/O0 — Bidirectional I/O pin 0 |
| 핀 2 | I/O1 — Bidirectional I/O pin 1 |
| 핀 3 | I/O2 — Bidirectional I/O pin 2 |
| 핀 4 | I/O3 — Bidirectional I/O pin 3 |
| 핀 5 | I/O4 — Bidirectional I/O pin 4 |
| 핀 6 | I/O5 — Bidirectional I/O pin 5 |
| 핀 7 | I/O6 — Bidirectional I/O pin 6 |
| 핀 8 | I/O7 — Bidirectional I/O pin 7 |
| 핀 9 | I/O8 — Bidirectional I/O pin 8 |
| 핀 10 | GND — Ground |
| 핀 11 | I/O9 — Bidirectional I/O pin 9 |
| 핀 12 | I/O10 — Bidirectional I/O pin 10 |
| 핀 13 | I/O11 — Bidirectional I/O pin 11 |
| 핀 14 | I/O12 — Bidirectional I/O pin 12 |
| 핀 15 | I/O13 — Bidirectional I/O pin 13 |
| 핀 16 | I/O14 — Bidirectional I/O pin 14 |
| 핀 17 | I/O15 — Bidirectional I/O pin 15 |
| 핀 18 | I/O16 — Bidirectional I/O pin 16 |
| 핀 19 | I/O17 — Bidirectional I/O pin 17 |
| 핀 20 | I/O18 — Bidirectional I/O pin 18 |
| 핀 21 | I/O19 — Bidirectional I/O pin 19 |
| 핀 22 | VCC — 5V supply voltage |
| 핀 23 | I/O20 — Bidirectional I/O pin 20 |
| 핀 24 | I/O21 — Bidirectional I/O pin 21 |
| 핀 25 | I/O22 — Bidirectional I/O pin 22 |
| 핀 26 | I/O23 — Bidirectional I/O pin 23 |
| 핀 27 | IN0 — Dedicated input pin 0 |
| 핀 28 | IN1/PRG — Dedicated input / programming control |
일반적인 애플리케이션
EP910LI-12 적합 용도: 6 애플리케이션s: 5V Bus Arbitration Logic, Address Decoder / Glue Logic, Peripheral Interface Controller, State Machine Controller, Legacy System Retrofit, Prototype and Design Iteration.
5V Bus Arbitration Logic
The EP910LI-12 fits 5V TTL bus-arbitration roles where its 12 ns combinatorial propagation delay ensures clean grant/acknowledge timing between CPU, DMA, and peripheral controllers. With 24 macrocells and 36 inputs, the device has ample capacity to encode multi-master priority schemes, request/grant handshakes, and interrupt steering logic on ISA, VME, or proprietary 5V backplanes. It pairs naturally with TTL bus transceivers (74LS245, 74F244) and the original 5V Intel CPU families (8086, 80186).
추천
Address Decoder / Glue Logic
The EP910LI-12 is well suited to legacy address-decoding and chip-select generation, replacing multiple 74LS138/139 PLD decoders with a single integrated solution. Its 36 inputs accommodate full 24-bit address plus control-signal fan-in, while the 12 ns tPD keeps chip-select skew under one ISA bus clock. This reduces board area and BOM count in 5V industrial controllers and VMEbus SBCs. The Classic EP910 architecture supports product-term sharing and OR-array folding for efficient decode trees.
추천
Peripheral Interface Controller
Use the EP910LI-12 to implement custom peripheral glue between a microcontroller and parallel I/O peripherals such as 8255 PPI, 8253 PIT, or 8237 DMA. The 12 ns propagation delay supports the bus timing of original PC/AT peripherals operating at 8 MHz, while the 24 I/O pins drive both address and data handshakes. The windowed ceramic package enables rapid firmware iteration during peripheral bring-up. Designers benefit from replacing dozens of TTL MSI chips with one EPLD, reducing power, cost, and PCB complexity.
추천
State Machine Controller
The EP910LI-12 implements Moore and Mealy state machines up to 24 states using its 24 macrocells, with the 12 ns tPD enabling deterministic sub-clock-cycle response in real-time control loops. Its EPROM configuration retains state-machine firmware through power cycles without external boot logic, and the 5V tolerance matches TTL sensor and actuator interfaces in industrial automation. Industrial-temperature (-40C to +85C) operation suits factory-floor deployment in motor control and process instrumentation.
추천
Legacy System Retrofit
The EP910LI-12 supports long-life retrofits of legacy 5V systems where modern CPLDs are pin-incompatible or require 3.3V core supplies that disturb existing analog front ends. Its 28-PLCC footprint matches classic 1990s motherboards, VMEbus cards, and industrial PLC modules, and Rochester Electronics maintains die-bank inventory for last-time-buy production. The windowed ceramic package also supports field re-programming via UV erasure, useful for systems where field updates must be possible without bootloader infrastructure.
추천
Prototype and Design Iteration
The EP910LI-12's windowed ceramic package makes it ideal for engineering prototypes, university teaching labs, and design iteration where UV erasure and reprogramming cycles are needed. Designers can validate state machines, decoders, and glue-logic equations against real hardware, then transition to the OTP plastic EP910LC-12 for production without changing the PCB footprint. This 'design with LI, ship with LC' workflow was the standard pattern for Classic EPLD development in the 1990s and remains in use today for EOL system maintenance.
추천
추천 제품 요약
엔지니어링 참조 데이터: EP910LI-12 — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | EP910LC-12 | EP910ILI-12 | EP910IPC-12 | EP910LC44-12 | EP910LI-35 |
|---|---|---|---|---|---|---|
| Package | 28-PLCC (windowed) | 28-PLCC (OTP plastic) | 28-PLCC (windowed) | 24-PDIP | 44-PLCC | 28-PLCC (windowed) |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Macrocells | 24 | 24 | 24 | 24 | 24 | 24 |
| Propagation Delay (tPD) | 12 ns | 12 ns | 12 ns | 12 ns | 12 ns | 35 ns |
| Maximum Frequency | 76.9 MHz | 76.9 MHz | 76.9 MHz | 76.9 MHz | 76.9 MHz | 30 MHz |
| Package Type | Windowed ceramic (erasable) | OTP plastic | Windowed ceramic | PDIP plastic | Plastic PLCC | Windowed ceramic |
| Operating Temperature | -40C to +85C (industrial) | 0C to +70C (commercial) | -40C to +85C (industrial) | -40C to +85C (industrial) | 0C to +70C (commercial) | -40C to +85C (industrial) |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Lifecycle Status | Obsolete | Obsolete (Rochester authorized) | Obsolete (Rochester active stock) | Obsolete | Obsolete | Obsolete (Rochester functional equivalent) |
주요 차별점
- Windowed ceramic package supports UV erasure for design iteration (vs EP910LC-12)
- Industrial temperature range across the same 28-PLCC footprint (vs EP910LC-12 (commercial 0C to +70C))
- 12 ns speed grade with 76.9 MHz fMAX (vs EP910LI-35)
설계 노트
The EP910LI-12 requires a clean 5V supply (4.75V to 5.25V) and benefits from bulk decoupling of 10 uF tantalum plus 0.1 uF ceramic placed within 25 mm of the VCC pin. Estimated: typical ICC is approximately 40 mA (200 mW / 5 V) at 76.9 MHz worst-case activity; power-down current falls to <1 mA when all inputs are static and clock edges are absent. Add a ferrite bead on the VCC feed for noise-sensitive analog sections that share the same 5V rail.
Drive all EP910LI-12 inputs to a defined logic level at power-up - floating inputs can draw several mA of shoot-through current and may latch the device into an indeterminate state. The 12 ns tPD is measured with a 50 pF load and 4 mA sink/source - keep output trace lengths under 50 mm or add a series damping resistor (22-33 ohm) for heavily loaded outputs. Avoid driving the EP910LI-12 outputs directly into long cables without a TTL buffer (74F244).
Do not confuse the EP910LI-12 (windowed ceramic, erasable) with the EP910LC-12 (plastic OTP) - both share the 28-PLCC footprint, but the OTP variant cannot be erased once programmed. Modern USB programmers (such as the Altera USB Blaster) do not support Classic EPLDs - use the legacy Altera MPU or third-party BP-1200/Data I/O programmer for production programming. UV erasure of the LI variant requires 20-30 minutes of exposure to an EPROM eraser at 12,000 uW/cm^2; under-erasures will produce unreliable reprogramming.
Estimated: at 5V VCC and 40 mA ICC, the EP910LI-12 dissipates 200 mW. The 28-PLCC ceramic package has a theta_JA of approximately 50 C/W (typical for windowed ceramic PLCC), yielding a junction temperature rise of 10 C above ambient at 200 mW - well within the industrial -40C to +85C operating envelope. No heatsink is required for normal operation. However, conformal coating on the quartz erase window can trap heat and should be avoided on the LI variant.
규정 준수 정보
The ceramic windowed 28-PLCC package contains lead-bearing solder and is not RoHS compliant - RoHS exemption applies for legacy EOL components under EU Directive 2011/65/EU Article 2(4)(c). For RoHS-compliant production, use the EP910LC-12 plastic PLCC variant. AEC-Q100 qualification is not available for Classic EPLDs; the part is not automotive-qualified.
