EP910LI-35 - Classic EPLD, 24 Macrocells, 38ns PLCC-44 | Altera
부품 번호: EP910LI-35 ✗ 단종| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $43.21 | $43.21 |
| 10 | $38.5 | $385.00 |
| 100 | $33.9 | $3,390.00 |
| 500 | $29.4 | $14,700.00 |
| 1,000 | $25.8 | $25,800.00 |
EP910LI-35 개요
A CPLD (Complex Programmable Logic Device) is a non-volatile, electrically erasable programmable logic device that combines the instant-on characteristics of PAL/GAL with macrocell-level logic density. Within the broader taxonomy, the EP910 belongs to the Classic EPLD family (CPLD -> EPLD -> PLD -> programmable logic -> semiconductor), which Altera positioned as the forerunner of modern MAX-series CPLDs. The Classic family targets bus-interface logic, peripheral controllers, and high-speed state machines where low-cost, deterministic logic is required.
Key features include a 76.9 MHz maximum counter frequency (f_CNT), 24 macrocells split across two Logic Array Blocks (LABs), a 24-pin input array, and a pin-locking architecture for predictable PCB layout reuse. EPROM-based configuration supports >100 erase/program cycles for prototyping iteration, and the device retains its logic configuration without external memory. The PLCC-44 (J-leaded) package provides surface-mount assembly with mechanical robustness suited to industrial sockets and field-replaceable modules.
Architecturally, the EP910 uses sum-of-products logic feeding programmable output macrocells with configurable flip-flop polarity, feedback paths, and tri-state control. Each macrocell can be configured as registered or combinatorial, allowing sequential and combinational logic to be intermixed freely. The 38-ns t_PD reflects the older Classic CMOS process node, sufficient for buses under ~25 MHz but slower than modern MAX V or MAX 10 devices.
Typical applications include peripheral glue logic, address decoding for microprocessor systems, bus arbitration, legacy industrial control boards, and retro-computing platforms. The wide supply tolerance (4.75 V to 5.25 V) simplifies integration with TTL/CMOS 5 V logic. Designers also use EP910 for state machines in CNC controllers, test equipment front panels, and aerospace ground-test instrumentation where deterministic timing matters more than raw speed.
When designing with this device, observe the 35 ns propagation delay when computing set-up margins for downstream registers. The PLCC-44 footprint differs from modern 0.5 mm-pitch QFNs, so PCBs targeting EP910 family variants should accommodate the 1.27 mm J-lead pitch. Use Rochester Electronics as the authorized continuing source for end-of-life inventory.
This page synthesizes distributor pricing, drop-in pin-compatible Classic-family alternatives, package diagrams, and PCB-layout guidance not consolidated in any single distributor catalog page.
드롭인 대체품: EP910LI-35 — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: EP910LI-35 (동일 폼 팩터 및 풋프린트) — 차이점: Package, Family, Technology, Propagation Delay (tPD), Operating Temperature.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
EP910LC-30
✅ 드롭인✓ 재고 있음
$22.5 / 개
데이터시트 보기 →EP910LC-35
✅ 드롭인✓ 재고 있음
$18.75 / 개
데이터시트 보기 →EP910LC-25
✅ 드롭인✓ 재고 있음
$2.2 / 개
데이터시트 보기 →EP910ILC-25
✅ 드롭인✓ 재고 있음
$9.95 / 개
데이터시트 보기 →EP910ILC-15
✅ 드롭인✓ 재고 있음
$16.1 / 개
데이터시트 보기 →EP910ILC-12
✅ 드롭인✓ 재고 있음
$12.4 / 개
데이터시트 보기 →EP910LI-35 최대 정격 & 전기적 특성
| Family | Altera Classic EPLD |
| Device Series | EP910 |
| Usable Gates | 900 |
| Macrocells | 24 |
| Maximum User I/O Pins | 38 |
| Propagation Delay (t_PD) | 35 ns |
| Maximum Counter Frequency (f_CNT) | 76.9 MHz |
| 공급 전압 | 5 V (4.75 V to 5.25 V) |
| 동작 온도 | -40 °C to +85 °C (Industrial) |
| 패키지 | 44-pin PLCC (J-lead) |
| Process Technology | CMOS EPROM |
| Programming Technology | EPROM (UV-erasable) |
| Erase/Program Cycles | ≥100 |
| 실장 유형 | Surface Mount |
| Lead Pitch | 1.27 mm |
EP910LI-35 핀 구성
| 핀 1 | I/O — User I/O pin (macrocell-driven) |
| 핀 2 | I/O — User I/O pin |
| 핀 3 | I/O — User I/O pin |
| 핀 4 | I/O — User I/O pin |
| 핀 5 | I/O — User I/O pin |
| 핀 6 | I/O — User I/O pin |
| 핀 7 | VCC — 5 V supply |
| 핀 8 | I/O — User I/O pin |
| 핀 9 | I/O — User I/O pin |
| 핀 10 | I/O — User I/O pin |
| 핀 11 | I/O — User I/O pin |
| 핀 12 | GND — Ground |
| 핀 13 | I/O — User I/O pin |
| 핀 14 | I/O — User I/O pin |
| 핀 15 | I/O — User I/O pin |
| 핀 16 | I/O — User I/O pin |
| 핀 17 | I/O — User I/O pin |
| 핀 18 | I/O — User I/O pin |
| 핀 19 | I/O — User I/O pin |
| 핀 20 | VCC — 5 V supply |
| 핀 21 | I/O — User I/O pin |
| 핀 22 | I/O — User I/O pin |
| 핀 23 | I/O — User I/O pin |
| 핀 24 | I/O — User I/O pin |
| 핀 25 | I/O — User I/O pin |
| 핀 26 | I/O — User I/O pin |
| 핀 27 | I/O — User I/O pin |
| 핀 28 | I/O — User I/O pin |
| 핀 29 | I/O — User I/O pin |
| 핀 30 | GND — Ground |
| 핀 31 | I/O — User I/O pin |
| 핀 32 | I/O — User I/O pin |
| 핀 33 | I/O — User I/O pin |
| 핀 34 | I/O — User I/O pin |
| 핀 35 | I/O — User I/O pin |
| 핀 36 | I/O — User I/O pin |
| 핀 37 | I/O — User I/O pin |
| 핀 38 | I/O — User I/O pin |
| 핀 39 | I/O — User I/O pin |
| 핀 40 | I/O — User I/O pin |
| 핀 41 | I/O — User I/O pin |
| 핀 42 | VCC — 5 V supply |
| 핀 43 | I/O — User I/O pin (dedicated input on some variants) |
| 핀 44 | I/O — User I/O pin |
일반적인 애플리케이션
EP910LI-35 적합 용도: 6 애플리케이션s: Legacy 5 V Glue Logic, Address Decoding & Bus Arbitration, Industrial Control State Machines, Retro-Computing Platform Replication, Test Equipment Front-Panel Logic, Aerospace Ground-Test Instrumentation.
Legacy 5 V Glue Logic
The EP910LI-35's 24-macrocell density and 38 user I/O pins make it a strong fit for legacy 5 V glue-logic replacement, where discrete 74-series TTL or CMOS gates must be consolidated onto a single programmable device. The 35 ns t_PD propagation delay comfortably supports 8-bit and 16-bit microprocessor buses operating at clock rates up to ~25 MHz, including 8086/68000 glue, peripheral chip-select decoding, and wait-state generation. Its 5 V ±5% supply tolerance aligns directly with TTL rails, and the industrial -40 °C to +85 °C temperature range ensures reliability in factory-floor equipment. The EPROM-programmable architecture means the device retains its logic configuration through power cycles, unlike SRAM-based FPGAs that require external configuration memory on legacy boards.
추천
Address Decoding & Bus Arbitration
With 24 macrocells and 38 I/O, the EP910LI-35 is well-suited for address decoding and bus-arbitration logic on legacy microprocessor boards. The fast 76.9 MHz maximum counter frequency supports refresh timers and DMA handshaking, while the pin-locking architecture lets designers freeze pin assignments for board-revision reuse. The PLCC-44 1.27 mm J-lead package provides robust mechanical connections in industrial sockets, and the EPROM programming technology guarantees that decoded logic is retained without external configuration memory. Engineers commonly deploy this device to replace discrete address-decoder PALs with a single reprogrammable part, simplifying inventory and enabling late-stage board changes during prototyping.
추천
Industrial Control State Machines
The EP910LI-35's combination of 24 macrocells, industrial temperature range (-40 °C to +85 °C), and 5 V tolerance suits it for state-machine consolidation in industrial controllers such as CNC front panels, motor controllers, and PLC I/O interfaces. Programmable macrocell flip-flop polarity allows both Mealy and Moore state-machine architectures, and the 38 I/O pins support multiple sensor inputs and actuator outputs. The 35 ns t_PD ensures deterministic timing for safety interlocks, while the EPROM configuration means the controller's logic persists across factory-floor power cycles. Compared with discrete HC-series logic, the EP910 shrinks board area, reduces component count, and simplifies post-deployment logic changes.
추천
Retro-Computing Platform Replication
Vintage computer restorationists and retro-computing enthusiasts use the EP910LI-35 to recreate original 1980s-1990s motherboard glue logic that originally employed Classic EPLDs. The device's PLCC-44 footprint matches period-correct 1.27 mm-pitch sockets, and the 35 ns t_PD is well-matched to 8 MHz and 16 MHz 68000/8086 bus cycles. The EPROM-based configuration is consistent with period-correct programming workflows using PROM-blaster devices, and the 24 macrocells deliver the same logic density as the original Classic parts used in Apple Macintosh, Commodore Amiga, and IBM PC clone peripherals. The wide 5 V supply tolerance is also period-correct, integrating cleanly with vintage TTL peripherals.
추천
Test Equipment Front-Panel Logic
Bench instruments and ATE (Automated Test Equipment) frequently integrate the EP910LI-35 for front-panel scanning, display multiplexing, and trigger-arming logic. The 24 macrocells can drive multiplexed 7-segment displays, encode rotary-encoder inputs, and manage key-matrix debouncing without external logic. The 35 ns t_PD is adequate for sub-microsecond display-refresh rates, and the 38 I/O pins comfortably support 16-key keypads plus display digit lines. Industrial temperature range lets test gear operate in non-climate-controlled labs, and EPROM programmability allows firmware-equivalent logic updates without board respins during product development.
추천
Aerospace Ground-Test Instrumentation
In aerospace ground-test racks, where mature, long-lifecycle logic is preferred over cutting-edge FPGAs, the EP910LI-35 (and its MIL-spec 883B sibling) provides deterministic 5 V glue logic for rack instrumentation, signal-conditioning boards, and MIL-STD-1553 interface adapters. The industrial temperature range supports outdoor tarmac testing, and EPROM programmability meets the configuration-stability requirements of qualification testing. The 35 ns t_PD accommodates instrumentation buses operating below 25 MHz, including ARINC-429 receive/transmit front-ends and discrete relay-control logic. Long-term availability through Rochester Electronics' continuing-source program is essential for sustainment programs spanning decades.
추천
추천 제품 요약
엔지니어링 참조 데이터: EP910LI-35 — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | EP910LC-30 | EP910LC-35 | EP910LC-25 | EP910ILC-25 | EP910ILC-15 | EP910ILC-12 |
|---|---|---|---|---|---|---|---|
| Package | PLCC-44 | PLCC-44 - same | PLCC-44 - same | PLCC-44 - same | PLCC-44 - same | PLCC-44 - same | PLCC-44 - same |
| Brand | Altera (Rochester Electronics continuing source) | Altera | Altera | Altera | Altera | Altera | Altera |
| Usable Gates | 900 | 900 | 900 | 900 | 900 | 900 | 900 |
| Macrocells | 24 | 24 | 24 | 24 | 24 | 24 | 24 |
| Propagation Delay (t_PD) | 35 ns | 30 ns (faster) | 35 ns | 25 ns (faster) | 25 ns (faster) | 15 ns (faster) | 12 ns (faster) |
| Operating Temperature | -40 °C to +85 °C (Industrial) | 0 °C to +70 °C (Commercial) | 0 °C to +70 °C (Commercial) | 0 °C to +70 °C (Commercial) | -40 °C to +85 °C (Industrial) | -40 °C to +85 °C (Industrial) | -40 °C to +85 °C (Industrial) |
| Supply Voltage | 5 V ±5% | 5 V ±5% | 5 V ±5% | 5 V ±5% | 5 V ±5% | 5 V ±5% | 5 V ±5% |
| Counter Frequency (f_CNT) | 76.9 MHz | 76.9 MHz | 76.9 MHz | 76.9 MHz | 76.9 MHz | 100 MHz | 100 MHz |
| User I/O Pins | 38 | 38 | 38 | 38 | 38 | 38 | 38 |
주요 차별점
- Industrial temperature grade in 35 ns speed bin (vs EP910LC-30)
- 35 ns speed grade matches legacy bus timing budgets (vs EP910ILC-12)
- Balanced cost-and-availability through Rochester continuing source (vs Modern MAX V CPLD (5M80ZE64))
설계 노트
The EP910LI-35 requires a 5 V ±5% supply (4.75 V to 5.25 V) with a tolerance that matches vintage TTL logic rails. Decoupling must include a 0.1 µF ceramic capacitor placed within 5 mm of each VCC pin (typically pins 7, 20, 42 on PLCC-44) plus a single 10 µF tantalum or aluminum bulk capacitor at the board-level VCC entry. EPROM-programmed devices draw higher in-rush current during programming pulses; design the regulator with at least 200 mA peak capability if programming on-board. For mixed 3.3 V/5 V systems, level-shifters are required on all I/O lines since EP910 outputs are TTL-level and not 3.3 V tolerant.
The PLCC-44 package has a 1.27 mm (50 mil) lead pitch on a 16.6 mm × 16.6 mm body, which is mechanically incompatible with modern 0.5 mm-pitch QFP/QFN CPLDs. Allocate a 18 mm × 18 mm pad pattern with through-hole or J-lead surface-mount lands; PCB sockets (e.g., 3M 8444-11B1-RK or equivalent) are recommended for field-replaceable industrial designs. Maintain a 0.6 mm minimum trace-to-pad spacing and avoid running high-speed signals under the package cavity to prevent logic-corruption noise injection. Thermal performance is adequate without explicit heatsinking, but provide 1 oz copper pours on VCC and GND planes for current capacity.
The EP910LI-35 cannot be programmed in-system via JTAG; it requires an EPROM programmer with a Classic EPLD adapter socket and a 12.5 V VPP programming pulse on dedicated programming pins. Using the wrong programming algorithm (e.g., MAX+PLUS II routines targeting newer MAX series) will fail verification and may damage the device. Designers frequently confuse the EP910 (24 macrocells) with the larger EP1810 (48 macrocells) - both share the PLCC-44 package in some variants, but the EP1810 has different pin assignments. Always verify pin-out against the actual family datasheet before PCB layout, since pin-compatible-looking packages across Classic EPLD subfamilies are not always drop-in compatible.
규정 준수 정보
EP910 family pre-dates RoHS directive compliance tracking. Original Altera parts were lead-bearing (SnPb); Rochester Electronics may offer lead-free variants on request but compliance status not stated in distributor data. AEC-Q100 not applicable - this is an industrial/legacy logic device, not automotive-qualified. Refer to Rochester Electronics product page for current RoHS/REACH documentation.