EP910PI-12T - 24 Macrocell Classic EPLD, 12ns tPD | Altera
부품 번호: EP910PI-12T ✗ 단종| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.95 | $1,395.00 |
| 500 | $11.8 | $5,900.00 |
| 1,000 | $9.95 | $9,950.00 |
EP910PI-12T 개요
An EPLD (Erasable Programmable Logic Device) is a one-time-or-UV-erasable PLD that preceded modern CPLDs and FPGAs. As a product category it sits between fixed logic gates and modern FPGAs in the programmable logic hierarchy: PLD -> EPLD -> CPLD -> FPGA. EPLDs typically offer macrocell-based combinational and registered logic with deterministic timing, non-volatile (UV-erasable) configuration, and instant-on behavior - making them suitable for legacy designs where simplicity and deterministic timing matter more than gate density.
Key features of the EP910PI-12T include 24 macrocells interconnected via a global programmable interconnect array, 24 I/O pins, and 12 dedicated inputs supporting two clock domains. Fabricated in CMOS technology, it offers a typical 15 ns pin-to-pin propagation delay (commercial) with the -12 speed grade being the faster variant in this part family. The device supports both combinatorial and registered logic with feedback, and is in-system programmable via a standard JEDEC programming interface.
Typical applications for the EP910PI-12T include address decoding, bus interfacing, state-machine control, and glue logic in legacy industrial, telecom, and embedded systems. Engineers selecting this part typically need exact timing behavior, deterministic logic, and pin compatibility with prior Altera Classic designs. It is fully compatible with industry-standard PLD development tools including the Altera MAX+PLUS II legacy flow.
Designers should note that the EP910 series is part of the mature Altera Classic EPLD line, now NRND/EOL for new designs. For new designs, consider MAX II, MAX V, or MAX 10 CPLDs as modern equivalents. The PDIP-40 package simplifies prototyping on through-hole PCBs but limits automated assembly. Pricing reflects legacy/obsolete status and limited supply.
드롭인 대체품: EP910PI-12T — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: EP910PI-12T (동일 폼 팩터 및 풋프린트) — 차이점: Package, Supply Voltage (VCC), Programming, RoHS Status, Technology.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
EP910PI-15T
✅ 드롭인✓ 재고 있음
$10.95 / 개
데이터시트 보기 →EP910PI-20T
✅ 드롭인✓ 재고 있음
$9.95 / 개
데이터시트 보기 →EP910PI-25
✅ 드롭인✓ 재고 있음
$10.95 / 개
데이터시트 보기 →EP910PI-30
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
EP910PC-30
✅ 드롭인✓ 재고 있음
$6.5 / 개
데이터시트 보기 →EP910PI-12T 최대 정격 & 전기적 특성
| Family | Altera Classic EPLD |
| Macrocells | 24 |
| Propagation Delay (tPD) | 12 ns |
| Maximum Operating Frequency | 76.9 MHz |
| Supply Voltage (VCC) | 5 V (4.75 V min, 5.25 V max) |
| I/O Pins | 24 |
| Dedicated Inputs | 12 |
| External Clock Inputs | 2 |
| Outputs | 24 |
| Terminals / Pin Count | 44 (PDIP-40 package pinout with NC pins) |
| 패키지 | 40-pin PDIP (Plastic DIP) |
| Process Technology | CMOS |
| 동작 온도 | 0C to +70C (commercial) |
| Programmable Technology | UV-erasable EPROM |
| Programming Interface | JEDEC-standard |
| RoHS 상태 | Non-compliant (legacy PDIP package, contains lead) |
| 수명 주기 상태 | NRND / EOL (mature legacy product) |
EP910PI-12T 핀 구성
| 핀 1 | I/O — Bidirectional I/O pin (macrocell) |
| 핀 2 | I/O — Bidirectional I/O pin (macrocell) |
| 핀 3 | I/O — Bidirectional I/O pin (macrocell) |
| 핀 4 | I/O — Bidirectional I/O pin (macrocell) |
| 핀 5 | I/O — Bidirectional I/O pin (macrocell) |
| 핀 6 | I/O — Bidirectional I/O pin (macrocell) |
| 핀 7 | I/O — Bidirectional I/O pin (macrocell) |
| 핀 8 | I/O — Bidirectional I/O pin (macrocell) |
| 핀 9 | I/O — Bidirectional I/O pin (macrocell) |
| 핀 10 | GND — Ground |
| 핀 11 | I/O — Bidirectional I/O pin (macrocell) |
| 핀 12 | I/O — Bidirectional I/O pin (macrocell) |
| 핀 13 | I/O — Bidirectional I/O pin (macrocell) |
| 핀 14 | I/O — Bidirectional I/O pin (macrocell) |
| 핀 15 | I/O — Bidirectional I/O pin (macrocell) |
| 핀 16 | I/O — Bidirectional I/O pin (macrocell) |
| 핀 17 | I/O — Bidirectional I/O pin (macrocell) |
| 핀 18 | I/O — Bidirectional I/O pin (macrocell) |
| 핀 19 | I/O — Bidirectional I/O pin (macrocell) |
| 핀 20 | I/O — Bidirectional I/O pin (macrocell) |
| 핀 21 | VCC — +5V supply |
| 핀 22 | I/O — Bidirectional I/O pin (macrocell) |
| 핀 23 | I/O — Bidirectional I/O pin (macrocell) |
| 핀 24 | I/O — Bidirectional I/O pin (macrocell) |
| 핀 25 | I/O — Bidirectional I/O pin (macrocell) |
| 핀 26 | I/O — Bidirectional I/O pin (macrocell) |
| 핀 27 | I/O — Bidirectional I/O pin (macrocell) |
| 핀 28 | IN — Dedicated input |
| 핀 29 | IN — Dedicated input |
| 핀 30 | IN — Dedicated input |
| 핀 31 | IN — Dedicated input |
| 핀 32 | IN — Dedicated input |
| 핀 33 | IN — Dedicated input |
| 핀 34 | CLK2/IN — Clock 2 or dedicated input |
| 핀 35 | CLK1/IN — Clock 1 or dedicated input |
| 핀 36 | IN — Dedicated input |
| 핀 37 | IN — Dedicated input |
| 핀 38 | IN — Dedicated input |
| 핀 39 | IN — Dedicated input |
| 핀 40 | OE/PRG — Output Enable / Programming control |
일반적인 애플리케이션
EP910PI-12T 적합 용도: 6 애플리케이션s: Address Decoding Glue Logic, State Machine Controllers, Bus Interface Logic, Legacy Industrial Control Systems, Custom Peripheral Emulation, Vintage Computing Retro-Projects.
Address Decoding Glue Logic
The EP910PI-12T's 24 macrocells and 12 ns tPD make it ideal for legacy address-decoding glue logic in x86, 68k, and similar microprocessor systems. Its deterministic timing eliminates race conditions in memory-mapped I/O designs, and the 24 dedicated inputs comfortably cover 24-bit address buses. The 12 ns propagation delay ensures decoder output propagation stays ahead of memory access times (typically 50-70 ns for legacy SRAM/DRAM), preventing system stalls. The CMOS 5V operation matches vintage TTL logic levels, allowing direct interfacing without level shifters. The PDIP-40 package simplifies breadboarding on ISA, VME, or STD-bus cards.
추천
State Machine Controllers
The EP910PI-12T's registered macrocells with feedback paths naturally implement Moore and Mealy state machines with up to 24 states per device. Its 76.9 MHz maximum toggle frequency supports high-speed sequential control loops, and the 12 ns tPD provides deterministic state-transition timing critical for industrial control systems. Two dedicated clock inputs allow separation of system clock and asynchronous event-driven logic. The 5V CMOS operation interfaces directly with TTL peripherals. Engineers favor the EP910PI-12T for legacy CNC, PLC, and motor-control state machines where deterministic behavior outweighs the need for modern flash-based CPLDs.
추천
Bus Interface Logic
The EP910PI-12T's 24 I/O pins and 12 dedicated inputs are well-matched to bus-interface logic for ISA, STD, VME, and similar legacy parallel buses. Its 12 ns tPD ensures clean bus arbitration and control-signal generation without metastability issues. The CMOS 5V interface is fully TTL-compatible, allowing direct connection to bus transceivers without buffering. Hardware engineers use the EP910PI-12T to implement custom bus-protocol converters, wait-state generators, and interrupt controllers. Its UV-erasable programmability allowed iterative debugging during development, though modern designs use JTAG-programmable MAX II CPLDs.
추천
Legacy Industrial Control Systems
The EP910PI-12T is widely deployed in legacy industrial control equipment (CNC machines, PLCs, robotics, test instrumentation) where its proven reliability and long-term availability through brokers matter more than modern features. Its commercial temperature range (0C to +70C) and PDIP-40 through-hole package suit industrial control cards mounted in climate-controlled enclosures. The deterministic timing, non-volatile EPROM configuration, and 24-macrocell density cover typical glue-logic blocks between microprocessors, memory, and I/O. Industrial engineers maintain inventory of EP910PI-12T to support installed equipment with 20+ year service lives.
추천
Custom Peripheral Emulation
The EP910PI-12T is used to emulate custom peripherals when the original ASIC or IC is obsolete. Its 24 macrocells can implement FIFO controllers, UARTs, timers, and protocol converters in a single device. The 12 ns tPD supports real-time emulation of peripherals with sub-100 ns timing budgets. Hardware engineers use the EP910PI-12T as a 'software-configurable hardware' solution to extend the life of legacy systems whose custom silicon is no longer available. This application is common in aerospace, defense, and medical equipment where long-term support contracts demand replacement parts over complete redesigns.
추천
Vintage Computing Retro-Projects
The EP910PI-12T is popular among vintage-computing hobbyists restoring classic workstations, arcade machines, and retro gaming hardware. Its 24-macrocell capacity suits glue-logic replacement on Apple II, Commodore 64, Atari ST, and similar 1980s-1990s era motherboards. The PDIP-40 package fits period-correct through-hole PCB designs. Hobbyists appreciate the Altera Classic EPLD's straightforward programming model (AND/OR array with macrocell flip-flops) which is well-documented and easy to learn. It enables reproduction of custom coprocessor cards, accelerator boards, and I/O expansions for classic systems.
추천
추천 제품 요약
엔지니어링 참조 데이터: EP910PI-12T — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | EP910PI-15T | EP910PI-20T | EP910PI-25 | EP910PI-30 |
|---|---|---|---|---|---|
| Package | PDIP-40 (Plastic DIP) | PDIP-40 - same | PDIP-40 - same | PDIP-40 - same | PDIP-40 - same |
| Brand | Altera (now Intel FPGA) | Altera - same | Altera - same | Altera - same | Altera - same |
| Family | Classic EPLD | Classic EPLD - same | Classic EPLD - same | Classic EPLD - same | Classic EPLD - same |
| Macrocells | 24 | 24 | 24 | 24 | 24 |
| Propagation Delay (tPD) | 12 ns | 15 ns | 20 ns | 25 ns | 30 ns |
| Max Frequency | 76.9 MHz | ~62 MHz | ~50 MHz | ~40 MHz | ~33 MHz |
| I/O Pins | 24 | 24 | 24 | 24 | 24 |
| Supply Voltage | 5V (4.75-5.25V) | 5V | 5V | 5V | 5V |
| Lifecycle Status | NRND/EOL | NRND/EOL | NRND/EOL | NRND/EOL | NRND/EOL |
주요 차별점
- Highest-speed grade in EP910 Classic EPLD PDIP-40 family (vs EP910PI-15T)
- Through-hole package option for legacy prototyping (vs EP910PC-30 (PLCC-44))
- Mature, well-documented Classic EPLD architecture (vs Modern MAX II (EPM240T100C5N))
설계 노트
Do not use the EP910PI-12T for new production designs. The Altera Classic EPLD family is NRND/EOL and pin-compatible second-source supply is extremely limited. For new designs, migrate to MAX II (EPM240/EPM570), MAX V (5M80ZE64/5M240ZE100), or MAX 10 (10M02/10M08/10M16) CPLDs. These provide non-volatile flash configuration, lower power, JTAG programming, and substantially larger macrocell counts while maintaining 5V-tolerant I/O options.
Estimated: at 5V supply and CMOS switching, the EP910PI-12T consumes approximately 50-150 mW active depending on toggle rate. At room temperature this is well within the commercial 0C to +70C operating range. Ensure adequate airflow in enclosed industrial cabinets. PDIP-40 plastic package thermal resistance is approximately 50 C/W - no heatsink needed for typical glue-logic use, but avoid sealed enclosures without ventilation.
Place 0.1 uF decoupling capacitors as close as possible to VCC pin 21 and GND pin 10. Add a 10 uF bulk capacitor on the supply rail near the device. Route all clock signals (CLK1, CLK2) with controlled impedance and keep them short to avoid ringing. The 5V CMOS outputs can drive 10-15 LSTTL loads; use buffers if driving larger fanouts. For through-hole PDIP-40 designs, allow 0.1 inch (2.54 mm) pitch and standard DIP socket footprint for field replacement.
규정 준수 정보
PDIP-40 package contains lead solder and is not RoHS-compliant. The Altera Classic EPLD family predates RoHS requirements. For RoHS-compliant alternatives use EP910LC or modern MAX-series CPLDs.
