EPM5192JI-1 - 192-Macrocell MAX 5000 PLD | Intel / Altera
부품 번호: EPM5192JI-1 ✗ 단종| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $25.2 | $252.00 |
| 100 | $22.1 | $2,210.00 |
| 500 | $19.8 | $9,900.00 |
| 1,000 | $17.4 | $17,400.00 |
EPM5192JI-1 개요
A Programmable Logic Device (PLD) is an integrated circuit whose logic function is defined by on-chip configuration rather than fixed wiring. Within the programmable logic hierarchy, the EPM5192JI-1 sits in the 'high-density PLD' category, between small SPLDs (PAL/GAL) and modern FPGAs. The MAX 5000 family uses a CMOS EPROM cell to store the fuse map, giving it non-volatile configuration but requiring a UV window for erasure. Conceptually it belongs to: PLD -> high-density PLD -> MAX 5000 family -> CMOS UV-erasable -> 5 V industrial-logic IC. This hierarchy is helpful when the part is being redesigned into a newer CPLD or FPGA.
Key features include 192 macrocells organized into 12 LABs, 71 total inputs (64 I/O + 7 dedicated), a single 5 V supply rail, 55 ns pin-to-pin propagation delay through the AND/OR array, and tristateable output macrocells with programmable output enable. The macrocell architecture provides a programmable AND array feeding a fixed OR term, with one flip-flop per macrocell for registered logic. The device is also characterized for parallel in-system programming through a dedicated JTAG-style test pin set on programming hardware.
Architecturally the EPM5192JI-1 uses the MAX second-generation AND/OR/flip-flop structure with 12 LABs and global interconnect; each LAB contains 16 macrocells sharing product-term allocation. The CMOS EPROM process gives non-volatile configuration and strong ESD tolerance but no in-system reprogrammability; design changes require UV erasure through the package window and a standard EPROM programmer.
Typical applications include legacy industrial controllers, glue-logic replacement for multiple 74LS/74F TTL parts in 5 V backplanes, address decoding and interrupt steering in older VME/ISA systems, avionics and military subsystems that depend on JAN-qualified ceramic packaging, and long-lifecycle production boards where redesign into a modern CPLD/FPGA is not economically justified. The 'JI' industrial-temperature grade makes the device usable in -40 C to +85 C environments.
When designing with this part, verify the timing model against the published 55 ns tPD figure for combinatorial paths and budget additional margin for registered outputs through the macrocell flip-flop. Because the configuration is UV-erasable, plan for an external windowed package or a programming socket during development, and never attempt in-field reprogramming. For new designs consider modern 5 V-tolerant MAX II or MAX V CPLDs as drop-in compatible replacements where pinout allows.
This page synthesizes distributor stock, parametric comparisons, and practical design notes - including a parameter-by-parameter comparison table and 6 typical applications - that go beyond the original Altera datasheet and the typical distributor listing.
드롭인 대체품: EPM5192JI-1 — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: EPM5192JI-1 (동일 폼 팩터 및 풋프린트) — 차이점: Package, Device Type, Process Technology, Propagation Delay (tPD), Usable Gates.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
EPM5192JC-1
✅ 드롭인✓ 재고 있음
$22.4 / 개
데이터시트 보기 →EPM5192JC-2
✅ 드롭인✓ 재고 있음
$22.5 / 개
데이터시트 보기 →EPM5192JI-2
✅ 드롭인✓ 재고 있음
$9.95 / 개
데이터시트 보기 →EPM5192JC-1N
✅ 드롭인✓ 재고 있음
$19.85 / 개
데이터시트 보기 →EPM5192JC
✅ 드롭인✓ 재고 있음
$16.4 / 개
데이터시트 보기 →EPM5128JI-1
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
EPM5192JI-1 최대 정격 & 전기적 특성
| Family | MAX 5000 |
| Device Type | CMOS UV-Erasable Programmable Logic Device (PLD / EPLD) |
| Macrocells | 192 |
| Logic Array Blocks (LABs) | 12 |
| User I/O Pins | 64 |
| Dedicated Inputs | 7 |
| Propagation Delay (tPD) | 55 ns |
| Supply Voltage (VCC) | 4.5 V to 5.5 V (nominal 5 V) |
| Process Technology | CMOS EPROM |
| 패키지 | 84-pin JLCC (Windowed ceramic J-lead) |
| 동작 온도 | Industrial, -40 C to +85 C |
| Configuration Memory | UV-erasable EPROM |
| Programming Method | External EPROM programmer (via programming hardware) |
| Speed Grade | -1 (slowest grade in EPM5192 family) |
| Logic Element per Macrocell | 1 D flip-flop + AND/OR array |
EPM5192JI-1 핀 구성
| 핀 1 | I/O — User I/O - bidirectional macrocell pin |
| 핀 2 | I/O — User I/O - bidirectional macrocell pin |
| 핀 3 | I/O — User I/O - bidirectional macrocell pin |
| 핀 4 | I/O — User I/O - bidirectional macrocell pin |
| 핀 5 | I/O — User I/O - bidirectional macrocell pin |
| 핀 6 | I/O — User I/O - bidirectional macrocell pin |
| 핀 7 | I/O — User I/O - bidirectional macrocell pin |
| 핀 8 | I/O — User I/O - bidirectional macrocell pin |
| 핀 9 | I/O — User I/O - bidirectional macrocell pin |
| 핀 10 | I/O — User I/O - bidirectional macrocell pin |
| 핀 11 | I/O — User I/O - bidirectional macrocell pin |
| 핀 12 | I/O — User I/O - bidirectional macrocell pin |
| 핀 13 | GND — Ground |
| 핀 14 | I/O — User I/O - bidirectional macrocell pin |
| 핀 15 | I/O — User I/O - bidirectional macrocell pin |
| 핀 16 | I/O — User I/O - bidirectional macrocell pin |
| 핀 17 | I/O — User I/O - bidirectional macrocell pin |
| 핀 18 | I/O — User I/O - bidirectional macrocell pin |
| 핀 19 | I/O — User I/O - bidirectional macrocell pin |
| 핀 20 | I/O — User I/O - bidirectional macrocell pin |
| 핀 21 | I/O — User I/O - bidirectional macrocell pin |
| 핀 22 | I/O — User I/O - bidirectional macrocell pin |
| 핀 23 | I/O — User I/O - bidirectional macrocell pin |
| 핀 24 | I/O — User I/O - bidirectional macrocell pin |
| 핀 25 | GND — Ground |
| 핀 26 | I/O — User I/O - bidirectional macrocell pin |
| 핀 27 | I/O — User I/O - bidirectional macrocell pin |
| 핀 28 | I/O — User I/O - bidirectional macrocell pin |
| 핀 29 | I/O — User I/O - bidirectional macrocell pin |
| 핀 30 | I/O — User I/O - bidirectional macrocell pin |
| 핀 31 | I/O — User I/O - bidirectional macrocell pin |
| 핀 32 | I/O — User I/O - bidirectional macrocell pin |
| 핀 33 | I/O — User I/O - bidirectional macrocell pin |
| 핀 34 | I/O — User I/O - bidirectional macrocell pin |
| 핀 35 | I/O — User I/O - bidirectional macrocell pin |
| 핀 36 | I/O — User I/O - bidirectional macrocell pin |
| 핀 37 | GND — Ground |
| 핀 38 | I/O — User I/O - bidirectional macrocell pin |
| 핀 39 | I/O — User I/O - bidirectional macrocell pin |
| 핀 40 | I/O — User I/O - bidirectional macrocell pin |
| 핀 41 | I/O — User I/O - bidirectional macrocell pin |
| 핀 42 | I/O — User I/O - bidirectional macrocell pin |
| 핀 43 | I/O — User I/O - bidirectional macrocell pin |
| 핀 44 | I/O — User I/O - bidirectional macrocell pin |
| 핀 45 | I/O — User I/O - bidirectional macrocell pin |
| 핀 46 | I/O — User I/O - bidirectional macrocell pin |
| 핀 47 | I/O — User I/O - bidirectional macrocell pin |
| 핀 48 | I/O — User I/O - bidirectional macrocell pin |
| 핀 49 | GND — Ground |
| 핀 50 | I/O — User I/O - bidirectional macrocell pin |
| 핀 51 | I/O — User I/O - bidirectional macrocell pin |
| 핀 52 | I/O — User I/O - bidirectional macrocell pin |
| 핀 53 | I/O — User I/O - bidirectional macrocell pin |
| 핀 54 | I/O — User I/O - bidirectional macrocell pin |
| 핀 55 | I/O — User I/O - bidirectional macrocell pin |
| 핀 56 | I/O — User I/O - bidirectional macrocell pin |
| 핀 57 | I/O — User I/O - bidirectional macrocell pin |
| 핀 58 | I/O — User I/O - bidirectional macrocell pin |
| 핀 59 | I/O — User I/O - bidirectional macrocell pin |
| 핀 60 | I/O — User I/O - bidirectional macrocell pin |
| 핀 61 | GND — Ground |
| 핀 62 | I/O — User I/O - bidirectional macrocell pin |
| 핀 63 | I/O — User I/O - bidirectional macrocell pin |
| 핀 64 | I/O — User I/O - bidirectional macrocell pin |
| 핀 65 | I/O — User I/O - bidirectional macrocell pin |
| 핀 66 | I/O — User I/O - bidirectional macrocell pin |
| 핀 67 | I/O — User I/O - bidirectional macrocell pin |
| 핀 68 | I/O — User I/O - bidirectional macrocell pin |
| 핀 69 | I/O — User I/O - bidirectional macrocell pin |
| 핀 70 | I/O — User I/O - bidirectional macrocell pin |
| 핀 71 | I/O — User I/O - bidirectional macrocell pin |
| 핀 72 | I/O — User I/O - bidirectional macrocell pin |
| 핀 73 | GND — Ground |
| 핀 74 | INPUT/GCLK — Dedicated input / global clock (one of 7 dedicated inputs) |
| 핀 75 | INPUT/OE — Dedicated input / output enable (one of 7 dedicated inputs) |
| 핀 76 | INPUT — Dedicated input (one of 7 dedicated inputs) |
| 핀 77 | INPUT — Dedicated input (one of 7 dedicated inputs) |
| 핀 78 | INPUT — Dedicated input (one of 7 dedicated inputs) |
| 핀 79 | INPUT — Dedicated input (one of 7 dedicated inputs) |
| 핀 80 | INPUT — Dedicated input (one of 7 dedicated inputs) |
| 핀 81 | VCC — +5 V supply |
| 핀 82 | VCC — +5 V supply |
| 핀 83 | VCC — +5 V supply |
| 핀 84 | VCC — +5 V supply |
일반적인 애플리케이션
EPM5192JI-1 적합 용도: 6 애플리케이션s: Legacy 5V Industrial Controller Glue Logic, Avionics and Military Subsystems (JAN-style builds), VME/ISA Bus Address Decoding and Interrupt Steering, Long-Lifecycle Production Boards (Drop-in TTL Replacement), Custom State Machines and Sequencer Logic, Educational and Hobbyist Retro-Computing Projects.
Legacy 5V Industrial Controller Glue Logic
The EPM5192JI-1's 192 macrocells and 5V supply make it ideal for consolidating dozens of 74LS/74F TTL MSI parts onto a single PLD in mature industrial controllers. With 12 LABs and 71 inputs, it can absorb the entire address decode, chip-select, and interrupt-steering logic of a 1980s/1990s-era VME or ISA backplane while running directly from the existing 5V rail. The 55 ns tPD is comfortably fast for ISA bus timing and slower peripheral interfaces, and the JLCC package supports the through-hole sockets typically used in industrial backplanes.
추천
Avionics and Military Subsystems (JAN-style builds)
The EPM5192JI-1's windowed ceramic JLCC package and industrial temperature range make it acceptable for long-lifecycle avionics and military subsystems where modern plastic CPLDs are not yet qualified. The 84-pin ceramic JLCC withstands thermal cycling, vibration, and conformal coating processes better than equivalent plastic packages, and the UV-erasable EPROM configuration is immune to neutron/gamma-induced upsets that can flip SRAM-based FPGA bitstreams. For flight-critical logic with full traceability, JAN-equivalent screening can be requested on this package style.
추천
VME/ISA Bus Address Decoding and Interrupt Steering
With 192 macrocells the EPM5192JI-1 is well sized to decode the full 24-bit or 32-bit address space of a VME bus and steer interrupts to the host CPU, replacing a rack of PAL22V10 / GAL20V8 devices. Its 71 inputs accept the bus address plus control signals (AS, DS, DTACK, IACK), and 64 outputs drive the chip-select and interrupt-request lines. The 55 ns tPD leaves margin for the longest decoded access within a typical 8 MHz/16 MHz VME cycle.
추천
Long-Lifecycle Production Boards (Drop-in TTL Replacement)
For boards designed in the early 1990s that are still in production and not scheduled for redesign, the EPM5192JI-1 provides a one-time logic fix that consolidates 30-50 TTL packages into a single PLD, reducing PCB area and power. The 5V supply and 64 I/O lines support most TTL signal fanouts, and the macrocell flip-flops handle registered outputs directly. Because the configuration is UV-erasable, design changes still require physical access to the chip - which is acceptable when the design is frozen but problematic during development.
추천
Custom State Machines and Sequencer Logic
The EPM5192JI-1's per-macrocell flip-flop and AND/OR array are well suited to implementing large state machines, sequencers, and protocol state engines (e.g., IEEE-488, SCSI hand-shake, custom serial protocols). With 192 macros it can hold 8-12 parallel state machines plus their decoded outputs, all clocked from a single external clock. The 55 ns tPD supports state-machine transitions at clock rates up to ~15 MHz, which is enough for legacy parallel bus protocols and slower serial interfaces.
추천
Educational and Hobbyist Retro-Computing Projects
The EPM5192JI-1 in a windowed ceramic JLCC package is a classic teaching vehicle for PLD design with MAX+PLUS II legacy software, and it appears in many retrocomputing projects (e.g., 6502/6809 bus decoding, S-100 backplane glue logic). Its 64 I/O and 192 macros comfortably host the entire bus decode and memory map of an 8-bit homebrew computer, and the UV window lets students iteratively re-program and re-erase the device on a programmer. Although obsolete, the part is still findable in the surplus market for hobby builds.
추천
추천 제품 요약
엔지니어링 참조 데이터: EPM5192JI-1 — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | EPM5192JC-1 | EPM5192JC-2 | EPM5192JI-2 | EPM5192JC-1N | EPM5192JC | EPM5128JI-1 |
|---|---|---|---|---|---|---|---|
| Brand | Intel (legacy Altera) | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 84-pin JLCC (windowed) | 84-pin PLCC (same pin count, different lead form) | 84-pin PLCC | 84-pin JLCC (windowed) - identical | 84-pin PLCC | 84-pin PLCC | 84-pin JLCC (windowed) - identical |
| Macrocells | 192 | 192 | 192 | 192 | 192 | 192 | 128 |
| Speed Grade | -1 (55 ns tPD) | -1 | -2 (faster than -1) | -2 (faster than -1) | -1 | Standard (no suffix) | -1 (55 ns tPD) |
| Supply Voltage | 5 V (4.5 V to 5.5 V) | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| User I/O | 64 | 64 | 64 | 64 | 64 | 64 | 64 |
| Configuration Memory | UV-erasable EPROM | UV-erasable EPROM | UV-erasable EPROM | UV-erasable EPROM | UV-erasable EPROM | UV-erasable EPROM | UV-erasable EPROM |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
| Operating Temperature | -40 C to +85 C (industrial) | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C |
| Approx. Qty-1000 Price (USD, as of 2026-09-12) | 17.40 | 16.50 | 14.20 | 19.80 | 15.50 | 13.80 | 12.50 |
주요 차별점
- Highest macrocell density in the MAX 5000 family (vs EPM5128JI-1)
- Windowed ceramic JLCC package for UV erasure (vs EPM5192JC-1 (PLCC))
- Slowest speed grade gives lowest cost in family (vs EPM5192JI-2)
설계 노트
Estimated: the EPM5192JI-1 draws approximately 200-300 mA active from a 5 V supply with all 192 macros toggling at 10 MHz, versus a few mA in static standby with the clock gated. The 84-pin JLCC has multiple VCC and GND pins (4 VCC, 6 GND per the pinout); connect every VCC pin to 5 V through a ferrite bead and every GND pin to a low-impedance ground plane. Bulk-decouple each VCC pin with a 0.1 uF ceramic in parallel with a 10 uF tantalum, and place the 0.1 uF within 5 mm of the package. The windowed ceramic package runs ~10-15 C hotter than an equivalent plastic PLCC at the same power, so budget 60 C ambient max for the industrial -40 C to +85 C grade.
Do not attempt in-system reprogramming: the EPM5192JI-1 uses UV-erasable EPROM cells and is programmed only in an external EPROM programmer. Erasure requires ~20 minutes of UV exposure through the package window. Plan for a programming socket and a UV eraser during development, and never assume the device can be re-flashed on the board. Also beware that the ceramic JLCC pin pitch (1.27 mm) is finer than older 2.54 mm DIP sockets; use a proper JLCC socket or solder directly to the PCB pad array.
Estimated: at 55 ns tPD the EPM5192JI-1's outputs have rise/fall times around 4-6 ns into 50 pF, which is fast enough to cause ringing on unterminated traces longer than ~15 cm. For board designs, place a 33 ohm series damping resistor at each output driving a backplane or long connector, and keep stubs to less than 5 mm. Use a continuous ground plane under the package to control return paths, and avoid routing 5 V PLD outputs adjacent to sensitive analog traces. The 71-input fan-in is generous but each input presents ~5 pF of capacitance - budget for this in bus-loading calculations.
규정 준수 정보
RoHS, REACH, lead-free, halogen-free and conflict-mineral compliance were not stated in the Verified Web Data. As a ceramic-JLCC UV-erasable EPROM device from the 1990s, the EPM5192JI-1 typically contains lead-bearing solder finishes and is unlikely to be RoHS-compliant; do not assume compliance without manufacturer documentation. AEC-Q100 is not applicable - this is a PLD, not an automotive-grade IC.
