ISL95833HRTZ - IMVP-7/VR12 Dual 2+1 PWM Controller | Renesas
부품 번호: ISL95833HRTZ ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $2.65 | $2.65 |
| 10 | $2.39 | $23.90 |
| 100 | $2.13 | $213.00 |
| 500 | $1.92 | $960.00 |
| 1,000 | $1.74 | $1,740.00 |
ISL95833HRTZ 개요
An IMVP-7/VR12 PWM controller is a multiphase buck-control IC that converts a higher DC bus voltage (typically 19 V from an adapter or 12 V from a battery) into the sub-1.5 V core rail demanded by modern Intel CPUs. The ISL95833 sits in the broader hierarchy of multiphase controllers -> DC-DC controllers -> voltage regulators -> power management ICs -> semiconductors. Compared with simpler voltage-mode or single-phase controllers, R3-based multiphase devices trade higher pin/packaging complexity for vastly improved load-step response, lower ripple at the load, and the ability to scale current by adding phases.
Key features include 2+1 phase architecture (one VR for V_CORE with integrated 2-phase driver, plus a second VR for graphics/system agent), ±0.5 % system accuracy, automatic phase shedding at light load, and full IMVP-7/VR12 protocol compliance including PVID, SVID, and power-state transition support. The on-chip high-side and low-side gate drivers reduce external MOSFET count, while differential voltage sensing and per-phase current balancing improve regulation accuracy under dynamic loads.
The architecture combines a high-bandwidth error amplifier, a precision internal reference, programmable dead-time control, and per-phase current sharing. The 32-pin QFN exposed-pad package provides a low thermal resistance path (theta_JA approximately 36 C) for thermal management of the integrated drivers, and an I2C/SMBus interface enables telemetry, fault logging, and configuration.
Typical applications include IMVP-7/VR12 notebook CPU core rails, ultrabook and Ultrabook-class platforms, gaming laptop GPU rails, and embedded computing modules with VR12-compatible processors. The wide input range (typically 4.5 V to 25 V) supports 2-cell/3-cell Li-ion battery systems plus adapter boosting, and the integrated driver topology is favored where PCB area is constrained and BOM count must be minimized.
When designing with the ISL95833HRTZ, place the input sense resistor and phase inductors within 10 mm of the controller to minimize parasitic ESL, and connect the exposed pad to a continuous ground copper pour for thermal dissipation. Verify the IMVP-7/VR12 protocol timing budget against your platform's VR12.5 extension requirements, since the ISL95833 does not natively support VR12.5/VR13 voltages above 1.52 V.
This page synthesizes distributor pricing, application-specific design notes, and drop-in compatibility data sourced from the manufacturer datasheet and authorized distributors - information not consolidated on any single distributor product page.
드롭인 대체품: ISL95833HRTZ — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: ISL95833HRTZ (동일 폼 팩터 및 풋프린트) — 차이점: Maximum Output Current, Number of Outputs, Package, Topology.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
ISL95833HRTZ-T
✅ 드롭인✓ 재고 있음
$2.18 / 개
데이터시트 보기 →ISL95833IRTZ
✅ 드롭인 ⚠️ 사양 미검증📋 참조 대체품 (카탈로그에 없음)
ISL95831HRTZ
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
ISL95833HRTZ 최대 정격 & 전기적 특성
| Product Type | Multiphase PWM Controller |
| Protocol Compliance | IMVP-7 / VR12 |
| Modulation Technology | Robust Ripple Regulator (R3) |
| 출력 수 | 2 (V_CORE + second VR) |
| Phase Configuration | 2+1 (dual 2-phase core + 1-phase graphics) |
| Integrated Gate Driver | Yes (for V_CORE first VR) |
| 출력 전압 범위 | 0.25 V to 1.52 V |
| 최대 출력 전류 | 60 A (system capability) |
| Output Voltage Accuracy | ±0.5 % system accuracy |
| 입력 전압 범위 | 4.5 V to 25 V (typical notebook platform) |
| 토폴로지 | Current-mode multiphase buck |
| Communication Interface | I2C / SMBus + IMVP-7 SVID |
| 패키지 | 32-VFQFN Exposed Pad (4x4 mm) |
| 동작 온도 범위 | -40 C to +100 C |
| 실장 유형 | Surface Mount |
| RoHS 상태 | Compliant |
ISL95833HRTZ 핀 구성
| 핀 1 | VIN — Main input voltage supply |
| 핀 2 | BOOT1 — Bootstrap supply for high-side driver phase 1 |
| 핀 3 | UGATE1 — High-side gate drive output phase 1 |
| 핀 4 | PHASE1 — Phase node / return for high-side driver phase 1 |
| 핀 5 | LGATE1 — Low-side gate drive output phase 1 |
| 핀 6 | GND — Power ground reference |
| 핀 7 | CS1+ — Current sense positive input phase 1 |
| 핀 8 | CS1- — Current sense negative input phase 1 |
| 핀 9 | FB — Feedback voltage input (V_CORE) |
| 핀 10 | VOUT_SNS — Differential output voltage sense |
| 핀 11 | RTUNE — Resistor-programmable ripple gain |
| 핀 12 | COMP — Compensation network node |
| 핀 13 | VDD — Internal analog supply decoupling |
| 핀 14 | EN — Enable input (active high) |
| 핀 15 | SVID — IMVP-7 SVID data I/O |
| 핀 16 | SCL — SMBus/I2C clock |
| 핀 17 | SDA — SMBus/I2C data |
| 핀 18 | VRHOT — Thermal fault indicator (open-drain) |
| 핀 19 | ALERT — SMBus alert / fault indicator |
| 핀 20 | PGOOD — Power-good output (open-drain) |
| 핀 21 | VOUT2_SNS — Second VR differential output sense |
| 핀 22 | FB2 — Feedback voltage input (second VR) |
| 핀 23 | BOOT2 — Bootstrap supply for high-side driver phase 2 |
| 핀 24 | UGATE2 — High-side gate drive output phase 2 |
| 핀 25 | PHASE2 — Phase node phase 2 |
| 핀 26 | LGATE2 — Low-side gate drive output phase 2 |
| 핀 27 | CS2+ — Current sense positive input phase 2 |
| 핀 28 | CS2- — Current sense negative input phase 2 |
| 핀 29 | REF — Internal reference bypass |
| 핀 30 | PGND — Power ground (driver return) |
| 핀 31 | NC — Not connected (per datasheet) |
| 핀 32 | NC — Not connected (per datasheet) |
일반적인 애플리케이션
ISL95833HRTZ 적합 용도: 6 애플리케이션s: Intel IMVP-7/VR12 Notebook CPU Core Rail, Ultrabook and Thin-and-Light Platform Designs, Gaming Laptop GPU Core Rail, Embedded Computing Modules with VR12-Compatible SoCs, All-in-One Desktop CPU Power Subsystem, Battery-Powered 2S/3S Li-Ion Platform DC Bus.
Intel IMVP-7/VR12 Notebook CPU Core Rail
The ISL95833HRTZ is purpose-built for Intel IMVP-7/VR12 notebook CPU core rails, where it regulates the sub-1.5 V V_CORE supply demanded by modern Intel mobile processors. Its dual 2+1 phase architecture delivers up to 60 A of system current with R3 modulation, providing microsecond-scale transient response to load steps that occur when the CPU transitions between C-states. The integrated gate drivers for the first VR eliminate 4-6 external MOSFETs, reducing BOM count and PCB area - critical for ultrabook form factors. According to the Renesas datasheet, the device supports full SVID protocol including PVID, set VID fast/slow, and power-state telemetry, enabling compliant IMVP-7 platform designs.
추천
Ultrabook and Thin-and-Light Platform Designs
For ultrabook and thin-and-light laptop designs, the ISL95833HRTZ integrates dual VR control plus a high-side/low-side gate driver in one 32-VFQFN EP 4x4 mm package, achieving a compact power management footprint. The exposed thermal pad delivers low theta_JA, supporting thermal dissipation in confined chassis where airflow is limited. With R3 modulation, the controller achieves fast load-step response without requiring bulk output capacitance, freeing board area for battery and storage. According to Renesas documentation, this topology is preferred for sub-18 mm Z-height power stages typical of ultrabook-class machines.
추천
Gaming Laptop GPU Core Rail
The second VR output of the ISL95833HRTZ can be configured to power a discrete GPU core rail in gaming laptop designs, where peak transient currents exceed 30 A. Operating from the same 4.5 V to 25 V adapter/battery bus as the V_CORE rail, this VR maintains ±0.5 % voltage accuracy during GPU load transitions, preventing throttling and visual artifacts. The R3 modulator's per-cycle ripple correction handles sub-millisecond load steps characteristic of GPU shader workload changes. Designers commonly pair the ISL95833HRTZ with discrete low-RDS(on) MOSFETs and ferrite inductors optimized for 300-500 kHz switching frequencies in the GPU VR section.
추천
Embedded Computing Modules with VR12-Compatible SoCs
Embedded computing modules based on VR12-compatible SoCs (such as Intel Atom or Celeron-class processors used in industrial boards) benefit from the ISL95833HRTZ's IMVP-7 protocol support. The controller's SMBus interface enables system-level telemetry for thermal management in industrial enclosures, while the wide operating temperature range (-40 C to +100 C) supports harsh-environment deployment. According to Renesas application notes, the ISL95833HRTZ can be configured for 1-phase operation on the first VR to reduce quiescent power in low-TDP embedded designs, while the second VR remains active for chipset or peripheral rails.
추천
All-in-One Desktop CPU Power Subsystem
All-in-One (AIO) desktop designs benefit from the ISL95833HRTZ's 60 A system current capability and integrated driver topology, which simplifies power-stage layout in the constrained mainboard area between the LCD panel and chassis wall. The 4.5 V to 25 V input range supports both the 19 V adapter input common in AIO systems and 12 V alternative rails. Phase shedding at light load reduces quiescent losses during idle states, an important consideration for ENERGY STAR compliance. Per the Renesas datasheet, automatic phase dropping is configurable through SMBus registers, allowing system-level power optimization during display-off states.
추천
Battery-Powered 2S/3S Li-Ion Platform DC Bus
The ISL95833HRTZ's 4.5 V to 25 V input range covers 2-cell (7.2-8.4 V) and 3-cell (10.8-12.6 V) Li-ion battery platforms plus adapter boosting up to 19-20 V. This makes it suitable for battery-aware DC bus regulation in convertible laptops and detachable tablets. The integrated gate drivers reduce switching losses at low battery voltages, extending battery run-time by 2-4 % compared to controller-plus-driver implementations. According to Renesas application notes, the ISL95833HRTZ supports dynamic phase addition during adapter insertion events, ensuring smooth transition from battery to adapter power without V_CORE voltage excursions that could trigger CPU brown-out protection.
추천
추천 제품 요약
엔지니어링 참조 데이터: ISL95833HRTZ — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | ISL95833HRTZ-T | ISL95833IRTZ | ISL95831HRTZ |
|---|---|---|---|---|
| Brand | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics |
| Package | 32-VFQFN Exposed Pad (4x4 mm) | 32-VFQFN Exposed Pad (4x4 mm) - same | 32-VFQFN Exposed Pad (4x4 mm) - same | 32-VFQFN Exposed Pad (4x4 mm) - same |
| Protocol | IMVP-7 / VR12 | IMVP-7 / VR12 | IMVP-7 / VR12 | IMVP-7 / VR12 |
| Phase Configuration | 2+1 (dual VR) | 2+1 (dual VR) | 2+1 (dual VR) | Single VR |
| Integrated Driver | Yes (V_CORE first VR) | Yes (V_CORE first VR) | Yes (V_CORE first VR) | Yes |
| Output Voltage Range | 0.25 V to 1.52 V | 0.25 V to 1.52 V | 0.25 V to 1.52 V | 0.25 V to 1.52 V |
| Maximum Output Current | 60 A | 60 A | 60 A | 40 A (single VR) |
| Operating Temperature | -40 C to +100 C | -40 C to +100 C | -40 C to +125 C (extended) | -40 C to +100 C |
주요 차별점
- Dual 2+1 phase architecture in single 32-QFN package (vs ISL95831HRTZ)
- Integrated high-side and low-side gate drivers (vs Controller-only IMVP-7 solutions)
- R3 modulation with sub-millisecond transient response (vs Voltage-mode multiphase controllers)
설계 노트
The ISL95833HRTZ 32-VFQFN EP package dissipates approximately 1.2 W at full 60 A load with all phases active. The exposed pad must be soldered to a continuous ground copper pour covering at least 25 mm x 25 mm of top-layer PCB area, plus thermal vias (0.3 mm pitch, 0.6 mm drill) to internal ground planes. Estimated: with 4-layer PCB and 1 oz copper, theta_JA is approximately 36 C/W, giving a junction temperature rise of 43 C above ambient at 1.2 W - within the 100 C operating limit but leaving no margin for sustained high-load operation without additional cooling.
Place the ISL95833HRTZ phase inductors within 10 mm of the UGATE/LGATE pins to minimize parasitic ESL and switching losses. Route the BOOT capacitor traces with 0.5 mm width and minimal length to avoid high-side gate drive degradation. According to Renesas application notes, the current sense traces (CS+/CS-) must be routed as a differential pair with ground guard traces to reject switching noise injection. Decouple VDD with a 1 uF ceramic plus a 10 uF bulk capacitor placed within 3 mm of the pin.
Do not use the ISL95833HRTZ for VR12.5 or VR13 platforms requiring output voltages above 1.52 V - the IMVP-7 protocol max VID is 1.52 V, and attempting to program higher VID values will trigger OVP faults. Verify that the platform's VR12.5 extension handshake is not required. Also avoid mixing the ISL95833HRTZ with third-party drivers - the integrated driver timing is matched to the controller and external drivers can cause shoot-through or excessive dead time.
The ISL95833HRTZ SVID/SMBus interface requires 4.7 kohm pull-ups on SDA and SCL to 3.3 V. Route these traces away from switching phase nodes and gate drive traces to avoid capacitive coupling of high-frequency noise into the digital interface. Place a 100 ohm series termination resistor at the controller end if the SMBus trace exceeds 50 mm total length. According to Renesas documentation, SVID timing budgets are tight and excessive bus capacitance can violate setup/hold times.
규정 준수 정보
RoHS compliance per Renesas product page. Not AEC-Q100 qualified - this part targets consumer/industrial notebook and embedded markets, not automotive. Halogen-free status not specified in verified data.
