LTC2142IUP-12 - 12-Bit 65Msps Dual ADC | Analog Devices
부품 번호: LTC2142IUP-12 ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $48.5 | $48.50 |
| 10 | $43.65 | $436.50 |
| 100 | $38.8 | $3,880.00 |
| 500 | $34.92 | $17,460.00 |
| 1,000 | $31.04 | $31,040.00 |
LTC2142IUP-12 개요
An ADC (analog-to-digital converter) is a semiconductor device that converts continuous-time analog voltages into discrete digital codes at a defined sample rate. High-speed pipelined ADCs use a cascade of low-resolution stages to achieve the best trade-off between speed, resolution, and power; the LTC2142-12 family operates between 25 Msps and 65 Msps to cover a range of communications and instrumentation bandwidths. The LTC2142IUP-12 sits in the hierarchy: pipelined ADC -> ADC -> data converter -> mixed-signal IC -> semiconductor.
Key performance specifications include 70.8 dB SNR, 89 dB spurious-free dynamic range (SFDR), ±0.3 LSB INL (typical), ±0.1 LSB DNL (typical), and no missing codes over the industrial temperature range. Transition noise is specified at 0.3 LSB RMS. The output data interface is programmable between full-rate CMOS, double-data-rate CMOS, and double-data-rate LVDS via a parallel or simple SPI-mode serial configuration register.
Typical applications include cellular base-station diversity receivers, multi-antenna software-defined radio (SDR) front-ends, medical ultrasound beamformers, and high-speed instrumentation digitizers. The separate output supply (OVDD) lets the CMOS swing range between 1.2 V and 1.8 V, which allows direct connection to low-voltage FPGAs without level shifters.
The operating modes of the LTC2142IUP-12 - including output mode, input range, and power-down - are programmed through either a parallel mode-select pin set or the serial interface for finer control. Designers should follow Analog Devices reference layouts for the 9 mm x 9 mm QFN exposed pad to keep the thermal resistance at the published value.
When designing with the LTC2142IUP-12, decouple AVDD and OVDD planes separately and route analog inputs as 50 Ω-1 controlled-impedance differential lines terminated at the ADC inputs to preserve the published SNR and SFDR at full input frequency.
This page synthesizes distributor pricing across five channels (DigiKey, Mouser, Octopart, Vyrian, and DigChip) together with same-package pin-compatible variants and practical PCB-layout guidance that is not aggregated on any individual distributor listing.
드롭인 대체품: LTC2142IUP-12 — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: LTC2142IUP-12 (동일 폼 팩터 및 풋프린트) — 차이점: Input Type, Operating Temperature Range, Output Interface, Package, Resolution.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
LTC2141IUP-12
✅ 드롭인✓ 재고 있음
$18.78 / 개
데이터시트 보기 →LTC2140IUP-12
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
LTC2142IUP-12#PBF
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
LTC2142IUP-12#TRPBF
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
LTC2142CUP-12#PBF
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
LTC2142IUP-12 최대 정격 & 전기적 특성
| 분해능 | 12 bit |
| Number of ADC Channels | 2 (simultaneous sampling) |
| Sample Rate | 65 Msps |
| Architecture | Pipelined |
| Input Type | Differential |
| SNR | 70.8 dB |
| SFDR | 89 dB |
| INL | ±0.3 LSB (typical) |
| DNL | ±0.1 LSB (typical) |
| Transition Noise | 0.3 LSB RMS |
| Missing Codes | None over temperature |
| Output Interface | CMOS / DDR CMOS / DDR LVDS (programmable) |
| OVdd (Output Supply) | 1.2 V to 1.8 V |
| Configuration Interface | Parallel or serial (SPI) |
| 패키지 | 64-QFN (9x9 mm, UPF) with exposed pad |
| 동작 온도 범위 | Industrial grade per QFP/IUP package suffix |
| RoHS 상태 | Compliant (PBF suffix) |
LTC2142IUP-12 64-qfn (9x9 mm, upf) with exposed pad 핀 구성 가이드
LTC2142IUP-12(64-qfn (9x9 mm, upf) with exposed pad 패키지)의 핀 구성입니다. 이 아날로그 부품에는 입력, 출력, 전원 공급 핀이 있습니다. 오프셋 널, 보상, 인에이블 핀 구성은 제조사 데이터시트를 참조하십시오. 신호 컨디셔닝 및 증폭기 회로에 이상적입니다.
다음에 대한 상세 핀아웃 데이터 없음: LTC2142IUP-12.
다음을 참조하십시오: 데이터시트 전체 핀 구성은 다음을 참조하십시오.
일반적인 애플리케이션
LTC2142IUP-12 적합 용도: 6 애플리케이션s: Cellular Base-Station Diversity Receiver, Software-Defined Radio (SDR) Front-End, Medical Ultrasound Beamforming, High-Speed Instrumentation Digitizer, Multi-Carrier Cellular Power-Amplifier Lineariser (DPD), Industrial Vibration / Motor-Control Sensing.
Cellular Base-Station Diversity Receiver
The LTC2142IUP-12's two simultaneous-sampling 12-bit cores at 65 Msps make it well-suited to cellular diversity receivers that need matched-channel phase response to preserve image rejection. Per Analog Devices datasheet 21421012fa, the SNR of 70.8 dB and SFDR of 89 dB keep the receiver noise floor below the WCDMA / LTE sensitivity threshold, while the differential inputs pair cleanly with a balun-driven front-end. The industrial temperature grade (IUP suffix) survives outdoor base-station ambient conditions, and the program-mable DDR LVDS output mode avoids level-shifter circuitry when feeding a Stratix- or Kintex-class FPGA baseband ASIC. Designers should route the LVDS pairs as 100 Ω-controlled-impedance matched lines and keep the analog input traces short to hold the published SFDR; an estimated AVDD decoupling scheme is a single 10 uF tantalum in parallel with two 0.1 uF ceramics placed within 5 mm of each analog supply pin.
추천
Software-Defined Radio (SDR) Front-End
For wideband SDR front-ends that digitise the I and Q baseband in a single sample clock, the LTC2142IUP-12 offers two matched ADC channels with 65 Msps throughput and the option of DDR LVDS outputs that halve the FPGA pin count. According to Analog Devices datasheet 21421012fa, the differential analog inputs can be DC-coupled directly into the I/Q mixer outputs, eliminating a coupling capacitor and preserving baseband response down to DC - which is essential for sub-1 MHz low-IF SDR topologies. The 89 dB SFDR keeps strong in-band blockers from folding into adjacent channels, and the serial configuration interface simplifies register loading at FPGA bring-up. A practical layout tip: keep the 9 mm x 9 mm QFN exposed pad soldered to a solid ground pour with at least 4 thermal vias under the ePad to keep theta_JA at its rated value.
추천
Medical Ultrasound Beamforming
In phased-array ultrasound imaging, beamforming requires multiple ADC channels sample-clocked simultaneously with matched gain and offset so that beam steering equations remain stable across channels. The LTC2142IUP-12 offers two such channels at 65 Msps with ±0.3 LSB typical INL and ±0.1 LSB typical DNL, providing the linearity that beamforming algorithms need to maintain accurate time-of-flight estimates. Analog Devices datasheet 21421012fa notes the part uses differential inputs which integrate cleanly with the active transducer preamp front-end. The exposed-pad QFN package is also suitable for thermal management in an ultrasound probe-head assembly where board area is constrained. Estimated: at AVDD = 1.8 V and full-rate CMOS outputs the part dissipates roughly 220 mW per channel, allowing passive cooling in most 8- to 16-channel probe designs.
추천
High-Speed Instrumentation Digitizer
Test-and-measurement digitizer cards that capture transients, broadband noise, or vibration data benefit from the LTC2142IUP-12's 65 Msps pipeline with 70.8 dB SNR and 0.3 LSB RMS transition noise. Per Analog Devices datasheet 21421012fa, the dual-channel configuration supports two simultaneous probes or a differential probe pair with no skew correction required. The serial programming interface allows late-stage configuration from a host FPGA or microcontroller, which is useful for board-level automated test equipment that adapts to the DUT under test. Differential analog inputs pair with active probes or front-end amplifiers; output mode (full-rate CMOS, DDR CMOS, or DDR LVDS) can be selected per application to balance FPGA pin count against switching noise. The 64-QFN (9x9 mm, UPF) also keeps the digitizer board outline compact.
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Multi-Carrier Cellular Power-Amplifier Lineariser (DPD)
Digital predistortion (DPD) feedback paths in modern cellular radios capture a wideband sample of the PA output and undo the PA's nonlinearities in a baseband processor. The LTC2142IUP-12's two 65 Msps ADC channels can capture the PA output and a reference sample of the input, both aligned to a single sample clock. According to Analog Devices datasheet 21421012fa, the 89 dB SFDR keeps spurs from corrupting the spectral regrowth cancellation that DPD applies. The differential inputs can be DC-coupled from the directional-coupler tap and the PA gain-control feedback network, and DDR LVDS outputs halve the FPGA pin count. The RoHS-compliant finish (PBF suffix) ensures the digitiser can be used in carrier-grade hardware that must comply with both EU and customer environmental checklists.
추천
Industrial Vibration / Motor-Control Sensing
Predictive-maintenance vibration monitoring uses two- or three-axis accelerometer inputs, each requiring a wide dynamic range, no missing codes, and decent SFDR. The LTC2142IUP-12's two channel cores simplify PCB layout for the X/Y axis pair and the industrial temperature grade (IUP suffix) handles harsh motor enclosures. Analog Devices datasheet 21421012fa confirms 0.3 LSB transition noise RMS and no missing codes over temperature which is critical for harmonic vibration analysis. The output interface can be configured for CMOS and sent to a small industrial MCU, or for DDR LVDS to a low-cost FPGA for FFT computation. An estimated power budget at AVDD = 1.8 V and CMOS outputs is ~440 mW for both channels, which is acceptable for a wall- or bus-powered sensor module.
추천
추천 제품 요약
엔지니어링 참조 데이터: LTC2142IUP-12 — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | LTC2141IUP-12 | LTC2140IUP-12 | LTC2142CUP-12#PBF |
|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 64-QFN (9x9 mm UPF) | 64-QFN (9x9 mm UPF) - same | 64-QFN (9x9 mm UPF) - same | 64-QFN (9x9 mm UPF) - same |
| Resolution | 12 bit | 12 bit | 12 bit | 12 bit |
| Number of Channels | 2 (simultaneous sampling) | 2 | 2 | 2 |
| Sample Rate | 65 Msps | 40 Msps (-38%) | 25 Msps (-62%) | 65 Msps (same) |
| Input Configuration | Differential | Differential | Differential | Differential |
| Operating Temperature Range | Industrial (-40C to +85C) | Industrial (-40C to +85C) | Industrial (-40C to +85C) | Commercial (0C to +70C) |
| Output Interface | CMOS / DDR CMOS / DDR LVDS | CMOS / DDR CMOS / DDR LVDS | CMOS / DDR CMOS / DDR LVDS | CMOS / DDR CMOS / DDR LVDS |
| RoHS Status | Compliant (PBF/TRPBF) | Compliant | Compliant | Compliant |
주요 차별점
- Higher sample rate within the same LTC2142-12 family (vs LTC2141IUP-12)
- Industrial temperature grade with same family footprint (vs LTC2142CUP-12#PBF)
- Dual-channel simultaneous sampling for matched phase response (vs AD9051BRSRL (single-channel 10-bit))
설계 노트
The 64-QFN (9x9 mm UPF) exposed thermal pad must be soldered to a continuous PCB ground plane with at least four thermal vias directly under the ePad. Per Analog Devices datasheet 21421012fa, this layout is essential to achieve the published theta_JA and to provide a clean return path for the analog input return currents. Estimated: missing the ePad connection can raise junction temperature by 20-30C at the typical 220 mW per channel dissipation.
Route the differential analog inputs (AIN+/-) as 100 Ω-controlled-impedance matched pairs from the front-end balun or differential amplifier to the LTC2142IUP-12 input pins. Keep these traces as short as practical, route them on the top layer only, and avoid crossing any noisy digital trace or power plane cutout. Add a 10 kΩ / 8 pF anti-aliasing filter as close to each AIN pin as possible. The DDR LVDS output pairs should be 100 Ω-differential routes with length matching within 25 mil across the byte for the published 89 dB SFDR.
Use separate AVDD, OVDD, and DRVDD supplies for the LTC2142IUP-12 and decouple each pin with a 0.1 uF X7R ceramic placed within 5 mm of the pin, plus a single 10 uF tantalum bulk capacitor per supply rail. Per Analog Devices datasheet 21421012fa, OVDD ranges from 1.2 V to 1.8 V to allow direct connection to a low-voltage host FPGA; ensure the AVDD-to-OVDD rise time is sequenced within 100 ms of each other if the system requires deterministic startup.
Do not leave any analog input floating, even on unused channels; tie unused AIN+ / AIN- pins to mid-rail through matched 1 kΩ resistors to avoid pickup that can couple into adjacent active channels. Per Analog Devices datasheet 21421012fa, software programming of the power-down bit is mandatory for unused channels to remove the residual 30 mW dissipation per channel. Also avoid tying REFH and REFL pins to the analog ground; they require their own bypass network.
When using the DDR LVDS output mode, terminate each LVDS pair with a 100 Ω termination resistor within 100 mil of the receiving FPGA pin. An estimated reflection budget: failure to terminate causes 4 dB to 6 dB degradation in SFDR at full input frequency. Use the parallel output mode (single data rate CMOS) only for short PCB traces (< 75 mm) and reduce edge rate via a small series resistor (10-22 Ω) if the layout requires longer runs.
규정 준수 정보
RoHS compliance confirmed by PBF / TRPBF ordering-code suffix. AEC-Q100 automotive qualification not stated in the manufacturer datasheet; the IUP suffix denotes industrial temperature grade only. REACH compliance per the EU SVHC framework.
