LTC2181IUP - 16-Bit 40Msps Dual ADC, DDR LVDS | Analog Devices
부품 번호: LTC2181IUP ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $34.65 | $346.50 |
| 100 | $30.8 | $3,080.00 |
| 500 | $27.95 | $13,975.00 |
| 1,000 | $25.2 | $25,200.00 |
LTC2181IUP 개요
An ADC (Analog-to-Digital Converter) is a data converter that samples continuous analog voltage signals and produces discrete digital codes. Within the broader semiconductor hierarchy, the LTC2181IUP belongs to the high-speed ADC family, which is itself a sub-category of data converters, sitting alongside DACs (Digital-to-Analog Converters) and CODECs. High-speed pipeline ADCs like the LTC2181 are the workhorse of communications, test and measurement, and defense signal chains where wide analog bandwidth and high dynamic range are required.
Key features include integrated bypass capacitance to reduce PCB complexity, selectable input ranges of 1 Vp-p to 2 Vp-p, an internal duty-cycle stabilizer that corrects for clock duty-cycle distortion, and a low-jitter clock receiver that accepts CMOS, LVDS, or sine-wave inputs. Each channel is independently controlled via a 3-wire SPI-compatible serial interface, allowing per-channel gain, offset, and phase calibration without external trim. The 64-lead QFN package with an exposed pad provides a thermal resistance (theta_JC) suitable for the device's low 100 mW per channel power dissipation.
The LTC2181's pipelined architecture is built around 16 internal stages with error correction, and its DDR LVDS digital interface transmits two data bits per clock cycle, halving the number of required output traces and easing PCB routing. The combination of low jitter (< 70 fs), high SNR, and selectable LVDS swing (350 mV or 700 mV) makes it well suited for driving FPGAs and ASICs over short board-to-board links.
Typical applications include cellular base-station receive paths, multiband, multimode digital receivers, antenna array processing, communications test equipment, and high-end imaging systems such as medical ultrasound and non-destructive flaw detection. The dual simultaneous-sampling architecture is particularly important for I/Q demodulation and for any system that requires phase-coherent acquisition of two signals.
When designing with the LTC2181IUP, place the 1.8 V analog decoupling capacitors within 5 mm of the AVDD pins and bond the exposed pad to a clean ground plane to keep digital switching currents out of the analog return path. The DDR LVDS output timing is referenced to the rising clock edge; be sure to use the same source-matched impedance (100 ohm differential) on all data and clock pairs to avoid inter-symbol jitter.
This page synthesizes distributor pricing, drop-in same-family alternatives (LTC2180, LTC2182), and practical layout guidance that is not contained in the bare manufacturer datasheet.
드롭인 대체품: LTC2181IUP — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: LTC2181IUP (동일 폼 팩터 및 풋프린트) — 차이점: Package, Resolution, SNR, Operating Temperature Range, Number of Channels.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
LTC2182IUP
✅ 드롭인✓ 재고 있음
$105.93 / 개
데이터시트 보기 →LTC2180IUP
✅ 드롭인✓ 재고 있음
$48 / 개
데이터시트 보기 →LTC2180CUP
✅ 드롭인✓ 재고 있음
$41.72 / 개
데이터시트 보기 →LTC2155CUP-12
✅ 드롭인✓ 재고 있음
$44.25 / 개
데이터시트 보기 →LTC2156IUP-14
✅ 드롭인✓ 재고 있음
$134.1 / 개
데이터시트 보기 →LTC2144IUP-14
✅ 드롭인✓ 재고 있음
$60.15 / 개
데이터시트 보기 →LTC2181IUP 최대 정격 & 전기적 특성
| Number of Bits | 16 |
| 샘플링 속도 | 40 Msps |
| Number of Channels | 2 (simultaneous sampling) |
| Architecture | Pipelined |
| Input Type | Differential |
| Selectable Input Range | 1 Vp-p to 2 Vp-p |
| Analog Supply Voltage | 1.8 V |
| Digital Output Interface | DDR LVDS |
| LVDS Swing Select | 350 mV or 700 mV |
| SNR (5 MHz input) | 77 dBFS |
| SFDR (5 MHz input) | 90 dBFS |
| Power Dissipation (per channel) | 100 mW |
| 동작 온도 | -40C to +85C |
| 패키지 | 64-QFN (9x9 mm) with exposed pad |
| Clock Duty-Cycle Stabilizer | Yes (internal) |
| Configuration Interface | SPI-compatible serial |
LTC2181IUP 핀 구성
| 핀 1 | GND — Ground |
| 핀 2 | INA+ — Channel A positive analog input |
| 핀 3 | INA- — Channel A negative analog input |
| 핀 4 | GND — Ground |
| 핀 5 | INB+ — Channel B positive analog input |
| 핀 6 | INB- — Channel B negative analog input |
| 핀 7 | GND — Ground |
| 핀 8 | AVDD — 1.8 V analog supply |
| 핀 9 | GND — Ground |
| 핀 10 | VCM — Common-mode voltage output |
| 핀 11 | AVDD — 1.8 V analog supply |
| 핀 12 | GND — Ground |
| 핀 13 | AVDD — 1.8 V analog supply |
| 핀 14 | SENSE — Voltage reference sense pin |
| 핀 15 | VREF — Voltage reference bypass |
| 핀 16 | GND — Ground |
| 핀 17 | OVDD — LVDS output driver supply |
| 핀 18 | GND — Ground |
| 핀 19 | CLK+ — Clock input positive |
| 핀 20 | CLK- — Clock input negative |
| 핀 21 | GND — Ground |
| 핀 22 | ENC+ — Encode clock positive (per datasheet) |
| 핀 23 | ENC- — Encode clock negative (per datasheet) |
| 핀 24 | GND — Ground |
| 핀 25 | OA0+ — Channel A LVDS data output bit 0 positive |
| 핀 26 | OA0- — Channel A LVDS data output bit 0 negative |
| 핀 27 | GND — Ground |
| 핀 28 | OA1+ — Channel A LVDS data output bit 1 positive |
| 핀 29 | OA1- — Channel A LVDS data output bit 1 negative |
| 핀 30 | GND — Ground |
| 핀 31 | OA2+ — Channel A LVDS data output bit 2 positive |
| 핀 32 | OA2- — Channel A LVDS data output bit 2 negative |
| 핀 33 | GND — Ground |
| 핀 34 | OA3+ — Channel A LVDS data output bit 3 positive |
| 핀 35 | OA3- — Channel A LVDS data output bit 3 negative |
| 핀 36 | GND — Ground |
| 핀 37 | OB0+ — Channel B LVDS data output bit 0 positive |
| 핀 38 | OB0- — Channel B LVDS data output bit 0 negative |
| 핀 39 | GND — Ground |
| 핀 40 | OB1+ — Channel B LVDS data output bit 1 positive |
| 핀 41 | OB1- — Channel B LVDS data output bit 1 negative |
| 핀 42 | GND — Ground |
| 핀 43 | OB2+ — Channel B LVDS data output bit 2 positive |
| 핀 44 | OB2- — Channel B LVDS data output bit 2 negative |
| 핀 45 | GND — Ground |
| 핀 46 | OB3+ — Channel B LVDS data output bit 3 positive |
| 핀 47 | OB3- — Channel B LVDS data output bit 3 negative |
| 핀 48 | GND — Ground |
| 핀 49 | FR+ — Frame output positive |
| 핀 50 | FR- — Frame output negative |
| 핀 51 | GND — Ground |
| 핀 52 | DCS+ — Duty-cycle stabilizer / data clock positive |
| 핀 53 | DCS- — Duty-cycle stabilizer / data clock negative |
| 핀 54 | GND — Ground |
| 핀 55 | CS — SPI chip select |
| 핀 56 | SCK — SPI serial clock |
| 핀 57 | SDI — SPI serial data input |
| 핀 58 | SDO — SPI serial data output |
| 핀 59 | GND — Ground |
| 핀 60 | OGND — Output driver ground |
| 핀 61 | OVDD — LVDS output driver supply |
| 핀 62 | GND — Ground |
| 핀 63 | AVDD — 1.8 V analog supply |
| 핀 64 | GND — Ground |
일반적인 애플리케이션
LTC2181IUP 적합 용도: 6 애플리케이션s: Cellular Base-Station Receive Path, Multiband Multimode Digital Receiver, Antenna Array Processing, Communications Test Equipment, Medical Ultrasound Imaging, Non-Destructive Flaw Detection.
Cellular Base-Station Receive Path
The LTC2181IUP's 77 dBFS SNR and 90 dBFS SFDR make it well suited for digitising multi-carrier LTE and 5G NR signals at the base-station antenna interface, where high dynamic range is required to detect weak users in the presence of strong in-band blockers. The dual simultaneous-sampling channels let designers capture two diversity or two polarisation paths with a single chip, halving board area versus a discrete dual-ADC design.
추천
Multiband Multimode Digital Receiver
The LTC2181IUP's 40 Msps sample rate is high enough to IF-sample signals in the 5-140 MHz range used by multiband software-defined radios, eliminating one or more downconversion stages. Its internal duty-cycle stabilizer tolerates non-50% clocks, and the 1.8 V single supply simplifies power-tree design. The dual channels let one chip serve as the I and Q paths of a complex mixer, reducing I/Q mismatch.
추천
Antenna Array Processing
Phased-array and MIMO systems demand phase-coherent multi-channel digitisation, and the LTC2181IUP's two simultaneous-sampling 16-bit channels provide the matched-channel acquisition needed for digital beamforming. With per-channel SPI gain and offset trim, the user can calibrate amplitude and phase mismatch in the digital domain. The 64-QFN package is small enough to place close to each antenna element, minimising analogue trace length.
추천
Communications Test Equipment
The 77 dBFS SNR, 90 dBFS SFDR, and selectable 1-2 Vp-p input range of the LTC2181IUP make it a strong fit for digitiser cards in spectrum analysers, signal generators, and production test racks. Its pipelined architecture delivers low latency suitable for closed-loop stimulus-response testing, and the DDR LVDS output feeds directly into FPGAs for real-time DSP such as FFT, demodulation, and EVM measurement.
추천
Medical Ultrasound Imaging
In medical ultrasound, each transducer channel requires a high-resolution, high-speed ADC, and the LTC2181IUP's two simultaneous-sampling channels let one IC service two transducer elements, halving the ADC count per probe. Its 16-bit resolution and low noise support the wide dynamic range needed to image both strong specular reflectors and subtle tissue echoes. The exposed-pad QFN package manages the modest 200 mW dissipation without a heatsink.
추천
Non-Destructive Flaw Detection
Industrial phased-array flaw detectors used in aerospace and pipeline inspection rely on the LTC2181IUP's dual simultaneous-sampling channels to capture transmit and receive echoes with matched timing, enabling accurate time-of-flight measurements. Its 40 Msps sample rate supports centre frequencies up to 20 MHz, and the 1.8 V supply rail simplifies battery-powered portable flaw detector designs used in the field.
추천
추천 제품 요약
엔지니어링 참조 데이터: LTC2181IUP — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | LTC2182IUP | LTC2180IUP | LTC2180CUP | LTC2156IUP-14 | LTC2144IUP-14 |
|---|---|---|---|---|---|---|
| Package | 64-QFN (9x9 mm) | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same |
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Resolution | 16-bit | 16-bit | 16-bit | 16-bit | 14-bit | 14-bit |
| Sampling Rate | 40 Msps | 65 Msps | 25 Msps | 25 Msps | 80 Msps | 80 Msps |
| Number of Channels | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) |
| Temperature Range | -40C to +85C (I grade) | -40C to +85C | -40C to +85C | 0C to +70C (C grade) | -40C to +85C | -40C to +85C |
주요 차별점
- Pin-compatible 25/40/65 Msps family enables single PCB design for multiple products (vs LTC2180IUP / LTC2182IUP)
- Higher SNR and SFDR than 14-bit dual ADCs in the same package (vs LTC2156IUP-14 / LTC2144IUP-14)
- Industrial -40C to +85C temperature grade at no extra cost vs commercial grade (vs LTC2180CUP)
설계 노트
Place the 1.8 V analog decoupling capacitors (typically 10 uF bulk + 0.1 uF ceramic) within 5 mm of the AVDD pins and bond the exposed pad to a clean ground plane with at least 9 thermal vias. The DDR LVDS data and clock pairs should be routed as 100 ohm differential microstrip with matched lengths to within 2 mm to avoid inter-symbol jitter, and should be guarded by adjacent ground traces on each side of the differential pair.
The AVDD and DVDD pins must be powered from the same low-noise 1.8 V LDO regulator (e.g., Analog Devices ADP1761) to prevent supply-noise coupling between channels. The OVDD pin can be tied to a separate supply if the FPGA LVDS receiver operates at a different voltage (1.8 V or 2.5 V). Add a small ferrite bead between the LDO output and the OVDD pin to break the digital switching return-current path.
Do not leave the SENSE pin floating - tie it to AVDD for internal reference or to VREF for external reference operation. The duty-cycle stabilizer (DCS) should be enabled for non-50% duty cycle clocks and disabled only when the user is supplying a clean 50% duty cycle clock. The exposed pad must be soldered to the PCB ground plane; failure to do so violates the thermal specification and may cause intermittent LVDS link errors.
Estimated: aperture jitter of the LTC2181IUP is < 70 fs RMS per the datasheet 218210f; at 40 Msps with a 140 MHz full-scale input, this contributes roughly 1 LSB of SNR degradation. To stay within budget, drive the CLK+/CLK- pins with a low-jitter clock source such as the ADF4351 or AD9528, and avoid sharing clock buffers between ADC and high-speed digital outputs.
규정 준수 정보
RoHS and lead-free per Analog Devices product page and PBF suffix convention. Not AEC-Q100 qualified - this part targets industrial-grade communications, not automotive. Halogen-free status not stated in the verified data.
