LTC2143CUP-12 - 12-Bit 80Msps Dual ADC | Analog Devices
부품 번호: LTC2143CUP-12 ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $37.46 | $37.46 |
| 10 | $34.1 | $341.00 |
| 100 | $28.5 | $2,850.00 |
| 500 | $24.75 | $12,375.00 |
| 1,000 | $22.1 | $22,100.00 |
LTC2143CUP-12 개요
An ADC (Analog-to-Digital Converter) is a mixed-signal integrated circuit that converts continuous analog waveforms into discrete digital codes for processing by microcontrollers, DSPs, or FPGAs. The pipelined ADC architecture — the hypernym hierarchy of which is: ADC -> data converter -> mixed-signal IC -> semiconductor — is the industry-preferred topology for sample rates from ~10 Msps to >500 Msps because it balances high speed, low power, and small die area. Dual-channel simultaneous-sampling ADCs such as the LTC2143-12 are critical for communications, radar, and I/Q demodulation where two related analog signals must be captured at the exact same instant.
Key specifications of the LTC2143CUP-12 include: 12-bit resolution, 80 Msps sample rate, 70.1 dB SNR, 88 dB SFDR, ±0.4 LSB INL (typical), 1.8 V analog/digital supply, and selectable full-scale input range of 1 Vp-p or 2 Vp-p. The serial LVDS output interface (DDR LVDS) supports up to 80 Msps with reduced pin count and excellent common-mode noise rejection. Power consumption is approximately 125 mW per channel at full speed, which is class-leading for the 80 Msps / 12-bit category.
Architecturally, the LTC2143-12 uses two interleaved 12-bit pipelined cores with a shared bandgap reference, an on-chip sample-and-hold amplifier, and a digital error-correction block. A self-calibration routine on power-up corrects capacitor mismatch and comparator offset, enabling the 88 dB SFDR performance without external calibration. The inputs are designed for differential drive to maximize even-order harmonic rejection; on-chip common-mode voltage generation simplifies AC-coupling with most modern op-amp drivers.
Typical applications for the LTC2143CUP-12 include multi-carrier GSM/EDGE and LTE base-station receivers, diversity radio IF digitization, radar and lidar front-ends, high-speed data acquisition systems, medical imaging (ultrasound beamformers), and communications test equipment. The wide input bandwidth (~750 MHz) also suits the digitizing of IF signals up to ~200 MHz without additional downconversion.
When designing with the LTC2143CUP-12, the most important layout consideration is the input network: use a transformer or differential op-amp driver such as the AD8138 with a 25 Ω series resistor at each analog input pin, and place the anti-aliasing RC network as close to the ADC as possible. Decouple the 1.8 V supply with 0.1 µF and 10 µF ceramic capacitors on every supply pin, and keep the LVDS output traces length-matched to within 5 mm to preserve DDR timing margins.
This page synthesizes distributor pricing, drop-in same-package alternatives, and design notes that go beyond the manufacturer datasheet — including a parameter-by-parameter comparison table and an explicit selection guide for choosing the LTC2143CUP-12 versus faster or higher-resolution members of the LTC2145-12 / LTC2144-12 / LTC2143-12 family.
드롭인 대체품: LTC2143CUP-12 — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: LTC2143CUP-12 (동일 폼 팩터 및 풋프린트) — 차이점: Package, Resolution, SFDR, SNR, Architecture.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
LTC2143CUP-12#TRPBF
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
LTC2143IUP-12#PBF
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
LTC2144CUP-12#PBF
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
LTC2145CUP-12#PBF
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
LTC2142IUP-14
✅ 드롭인✓ 재고 있음
$34.71 / 개
데이터시트 보기 →ISLA214P25IRZ
✅ 드롭인✓ 재고 있음
$24.9 / 개
데이터시트 보기 →LTC2143CUP-12 최대 정격 & 전기적 특성
| Manufacturer | Analog Devices |
| MPN | LTC2143CUP-12 |
| Description | 12-Bit, 80 Msps, Low-Power Dual ADC |
| 분해능 | 12 bit |
| Number of Channels | 2 (simultaneous sampling) |
| Sample Rate | 80 Msps |
| Architecture | Pipelined |
| Input Type | Differential |
| Supply Voltage (Analog) | 1.8 V |
| Supply Voltage (Digital) | 1.8 V |
| Supply Voltage (Output Buffer / LVDS) | 1.8 V (optional) |
| Input Full-Scale Range | 1 Vp-p or 2 Vp-p (selectable) |
| Analog Input Bandwidth | 750 MHz |
| SNR | 70.1 dB |
| SFDR | 88 dB |
| INL (typical) | ±0.4 LSB |
| Power Consumption | ~125 mW per channel at 80 Msps |
| Output Interface | CMOS / DDR LVDS (selectable) |
| On-Chip Reference | Yes (internal bandgap) |
| 동작 온도 범위 | 0°C to +70°C (C-grade) |
| 패키지 | 64-QFN (9x9 mm) with exposed pad |
| 실장 유형 | Surface Mount |
| RoHS Compliance | Yes |
LTC2143CUP-12 64-qfn (9x9 mm) with exposed pad 핀 구성 가이드
LTC2143CUP-12(64-qfn (9x9 mm) with exposed pad 패키지)의 핀 구성입니다. 이 아날로그 부품에는 입력, 출력, 전원 공급 핀이 있습니다. 오프셋 널, 보상, 인에이블 핀 구성은 제조사 데이터시트를 참조하십시오. 신호 컨디셔닝 및 증폭기 회로에 이상적입니다.
다음에 대한 상세 핀아웃 데이터 없음: LTC2143CUP-12.
다음을 참조하십시오: 데이터시트 전체 핀 구성은 다음을 참조하십시오.
일반적인 애플리케이션
LTC2143CUP-12 적합 용도: 7 애플리케이션s: Multi-Carrier Cellular Base-Station Receivers, Diversity Radio IF Digitization, Radar and Lidar Front-End Digitization, High-Speed Data Acquisition Systems, Medical Ultrasound Beamformers, Communications Test and Measurement, Software Defined Radio (SDR) Platforms.
Multi-Carrier Cellular Base-Station Receivers
The LTC2143CUP-12 is well-suited for multi-carrier GSM/EDGE and LTE base-station receiver IF digitization. The dual simultaneous-sampling channels allow direct capture of I and Q baseband signals at the same instant, eliminating quadrature skew that would otherwise corrupt the constellation. With 70.1 dB SNR and 88 dB SFDR, the part easily resolves carriers at -78 dBm while still tolerating blocking signals up to -10 dBm. The 80 Msps sample rate supports bandwidths up to 35 MHz per channel, and the 1.8 V single-supply operation simplifies the radio board. Use the LVDS output mode to drive an FPGA crossbar with minimum EMI.
추천
Diversity Radio IF Digitization
For diversity radio receivers with two antenna paths, the LTC2143CUP-12's two matched ADC cores capture both channels at exactly the same instant — critical for maximal-ratio combining. The 70.1 dB SNR supports 64-QAM demodulation with margin, and the 750 MHz analog input bandwidth covers IF frequencies up to ~200 MHz, allowing the use of a low-IF architecture with no second downconversion. The selectable 1 Vp-p / 2 Vp-p input range accommodates different SAW filter output levels. Power is ~250 mW total at full rate, enabling fanless outdoor radio unit (ODU) deployments.
추천
Radar and Lidar Front-End Digitization
The LTC2143CUP-12 is a strong fit for phased-array radar and lidar front-end digitization where two matched channels are required. The 12-bit resolution provides ~72 dB of dynamic range — sufficient for short-range automotive radar and most industrial lidar systems. The wide 750 MHz analog input bandwidth handles the wideband IF signals of FMCW radar directly, and the dual channels digitize I/Q pairs or two adjacent array elements with zero inter-channel skew. The 64-QFN (9x9) package is small enough to place one ADC per array element, supporting compact tile designs.
추천
High-Speed Data Acquisition Systems
Portable and laboratory data acquisition systems benefit from the LTC2143CUP-12's low 250 mW total power dissipation, allowing sealed enclosures without active cooling. The dual channels digitize two synchronized sensor inputs (strain gauge + accelerometer, for example) at 80 Msps, capturing transient events that would be missed by slower multiplexed ADCs. The LVDS output mode connects directly to FPGAs, where the data is packed, buffered, and pushed to DDR memory or USB 3.0 for host transfer. The 1.8 V supply also simplifies power-tree design on modern FPGA-based instruments.
추천
Medical Ultrasound Beamformers
Portable and mid-tier ultrasound imaging systems use the LTC2143CUP-12 to digitize transducer element returns at the channel level, before beamforming in the FPGA. The dual-channel integration reduces board area and BOM cost versus two single-channel ADCs, and the simultaneous-sampling architecture is mandatory for proper beamforming — any inter-channel skew translates directly into image artifacts. The 70.1 dB SNR supports the 60 dB dynamic range required for clinical abdominal and cardiac imaging, and the 1.8 V supply enables battery-powered cart-based systems with 4+ hours of runtime.
추천
Communications Test and Measurement
Vector signal analyzers, arbitrary waveform generators, and wireless test sets use the LTC2143CUP-12 to capture modulated signals for EVM, ACPR, and spectrum analysis. The 70.1 dB SNR and 88 dB SFDR enable EVM measurements below 1% on QAM signals, and the dual channels allow simultaneous capture of the device-under-test output and a reference channel for closed-loop calibration. The wide input bandwidth covers test vectors up to ~200 MHz IF, and the compact 64-QFN package fits into 1U rack-mount instrument form factors with high channel density.
추천
Software Defined Radio (SDR) Platforms
Wideband SDR platforms for amateur radio, public safety, and signal intelligence use the LTC2143CUP-12 to digitize IF or direct-conversion baseband signals. The two channels cover I/Q of a single tuner, or two independent tuners in time-division mode. The 80 Msps sample rate is sufficient for capturing 35 MHz of instantaneous bandwidth, and the 1.8 V single supply simplifies USB-powered portable SDR dongles. The CMOS output mode also works directly with lower-cost MCUs and DSPs for software-only demodulation pipelines.
추천
추천 제품 요약
엔지니어링 참조 데이터: LTC2143CUP-12 — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | LTC2143CUP-12#TRPBF | LTC2143IUP-12#PBF | LTC2144CUP-12#PBF | LTC2145CUP-12#PBF | LTC2142IUP-14 |
|---|---|---|---|---|---|---|
| Package | 64-QFN (9x9 mm) | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same |
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Resolution | 12 bit | 12 bit | 12 bit | 12 bit | 12 bit | 14 bit |
| Sample Rate | 80 Msps | 80 Msps | 80 Msps | 105 Msps | 125 Msps | 65 Msps |
| Number of Channels | 2 | 2 | 2 | 2 | 2 | 2 |
| Supply Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Operating Temperature | 0°C to +70°C | 0°C to +70°C | -40°C to +85°C | 0°C to +70°C | 0°C to +70°C | -40°C to +85°C |
| Power Consumption (per channel) | ~125 mW | ~125 mW | ~125 mW | ~160 mW | ~190 mW | ~110 mW |
| Output Interface | CMOS / DDR LVDS | CMOS / DDR LVDS | CMOS / DDR LVDS | CMOS / DDR LVDS | CMOS / DDR LVDS | CMOS / DDR LVDS |
주요 차별점
- Lowest power 12-bit 80 Msps dual ADC in its class (vs LTC2144CUP-12#PBF)
- Industrial-temperature drop-in via the 'I' grade variant (vs LTC2143CUP-12#PBF (commercial))
- Selectable 1 Vp-p / 2 Vp-p input range matches a wider range of drivers (vs LTC2159IUK)
설계 노트
Place 0.1 µF X7R ceramic bypass capacitors on every AVDD and DVDD pin, with one 10 µF bulk ceramic on each rail, all within 2 mm of the supply pin. Use a continuous ground plane on layer 2 directly under the ADC, and stitch the exposed pad to ground with at least 9 thermal vias (0.3 mm drill, 0.6 mm pad) for a θJA of approximately 28 °C/W. Estimated: the 9-via pattern is the minimum recommended for 1 W dissipation at +70 °C ambient; thermal performance was calculated based on the 64-QFN (9x9 mm) family datasheet θJA curve, not the specific LTC2143CUP-12 datasheet figure.
Keep the analog input traces (AIN+/AIN- pairs) length-matched to within 0.5 mm and surrounded by a continuous ground fill on both sides. The LVDS output pairs (D+/D-) should also be length-matched to within 5 mm and routed on a single inner layer with 100 Ω differential impedance. Route the encode clock (ENC+/ENC-) on the same layer as the analog inputs but kept physically separated by at least 5 mm of ground fill to avoid coupling. Reference: the 21454312fa datasheet PCB layout guidelines, page 22.
Place a 25 Ω series resistor close to each analog input pin (within 3 mm) to damp the sample-and-hold kick and flatten the input network Q. Drive the ADC differentially using a balun (for AC-coupled IF) or a differential op-amp such as the AD8138 or ADA4937-1. Set the common-mode voltage of the driver to the VCM output pin of the ADC (typically 0.9 V at 1.8 V supply). Avoid running digital LVDS traces over or under the analog input traces — use orthogonal routing on adjacent layers.
Do not leave the LVDS/CMOS mode-select pin floating — strap it to logic-high or logic-low through a 10 kΩ resistor at the ADC pin. The internal reference should be decoupled with a 2.2 µF X5R capacitor at the REFCOMP pin; omitting this capacitor degrades SNR by 3-5 dB. Do not exceed the 1.8 V absolute maximum on any supply pin, even transiently, or the device may latch up. The SHDN pin is active-low; pull it high through a 100 kΩ resistor to enable.
규정 준수 정보
RoHS compliant per Analog Devices product page and DigiKey listing. Not AEC-Q100 qualified; automotive applications should use the AD9268XCPZ-125 or similar AEC-Q100-grade ADC. Halogen-free status is not explicitly stated in the verified data; halogen-free status is unknown and should be confirmed with ADI for green-product design requirements.
