LTC2206IUK - 16-Bit 80Msps ADC, PGA, 48-QFN | Analog Devices
부품 번호: LTC2206IUK ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $35.2 | $352.00 |
| 100 | $31 | $3,100.00 |
| 500 | $27.8 | $13,900.00 |
| 1,000 | $24.95 | $24,950.00 |
LTC2206IUK 개요
An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that converts continuous-time, continuous-amplitude analog signals into discrete-time digital codes. Pipelined ADCs use multiple stages of low-resolution flash sub-converters with inter-stage sample-and-hold and digital error correction to achieve high sampling rates while maintaining resolution - a hierarchy of: ADC -> data converter -> mixed-signal IC -> semiconductor. The LTC2206 family sits within this lineage as a wideband, high-linearity member.
Key features include an integrated PGA (programmable gain amplifier) front end with adjustable input range (1 Vpp to 2.25 Vpp, typical), 77.5 dB SNR at 30 MHz input, 90 dB SFDR, internal bypassable reference, and CMOS-compatible outputs. The datasheet specifies a 0.5 ps RMS typical aperture jitter for accurate undersampling of IF signals. Single 3.3 V supply operation and LVCMOS/CMOS-compatible digital outputs simplify interface design.
The pipelined architecture provides excellent spurious-free dynamic range (SFDR) over a wide input bandwidth, supporting multi-carrier communications and radar IF digitisation. A built-in dither generator improves low-level linearity. Optional LVDS output and an internal data randomizer (on related LTC2207) further reduce idle tones for sensitive spectral measurements.
Typical applications include cellular base-station receiver IF digitisation, software-defined radio (SDR), test and measurement equipment, cable head-end equipment, and broadband communications links. Two recommended evaluation companion parts are the LT6202 low-noise op amp (ADC driver) and the LTC2207IUK for higher 105 Msps throughput in adjacent frequency plans.
When designing with this ADC, pay close attention to input common-mode biasing and use a differential transformer driver or matched op-amps to preserve SFDR at high IF. Encode clock jitter must remain under the part's 0.5 ps RMS aperture jitter budget, and the analog input band-pass filter affects overall system noise figure.
This page synthesizes distributor pricing, drop-in same-family alternatives, and design guidance not aggregated on the manufacturer datasheet - enabling faster board bring-up and a clearer cross-reference view across the LTC2205/2206/2207 family.
드롭인 대체품: LTC2206IUK — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: LTC2206IUK (동일 폼 팩터 및 풋프린트) — 차이점: Package, SFDR, SNR, RoHS Status, Sample Rate.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
LTC2207IUK
✅ 드롭인✓ 재고 있음
$51.4 / 개
데이터시트 보기 →LTC2206IUK-14
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
LTC2205IUK
✅ 드롭인✓ 재고 있음
$70.56 / 개
데이터시트 보기 →LTC2206CUK
✅ 드롭인✓ 재고 있음
$49.5 / 개
데이터시트 보기 →LTC2206IUK#PBF
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
LTC2206IUK 최대 정격 & 전기적 특성
| 분해능 | 16 bit |
| Sample Rate | 80 Msps |
| Number of Inputs | 1 |
| Architecture | Pipelined |
| Input Frequency Range | Up to 700 MHz |
| Input Range (PGA) | Adjustable, programmable gain front end |
| SNR (at 30 MHz input) | 77.5 dB |
| SFDR | 90 dB |
| Aperture Jitter | 0.5 ps RMS (typical) |
| 공급 전압 | 3.3 V single supply |
| Output Format | Parallel CMOS |
| Reference | Internal, bypassable |
| 패키지 | 48-QFN (7x7 mm) |
| 동작 온도 범위 | -40 C to +85 C (industrial, I suffix) |
| 실장 유형 | Surface Mount |
| RoHS 상태 | Compliant |
LTC2206IUK 핀 구성
| 핀 1 | GND — Ground |
| 핀 2 | AIN+ — Differential analog input positive |
| 핀 3 | AIN- — Differential analog input negative |
| 핀 4 | SENSE — Reference programming pin |
| 핀 5 | VREF — Internal reference bypass |
| 핀 6 | VDD — Analog 3.3V supply |
| 핀 7 | OVDD — Digital 3.3V supply |
| 핀 8 | GND — Ground |
| 핀 9 | D0 — CMOS data output bit 0 (LSB) |
| 핀 10 | D1 — CMOS data output bit 1 |
| 핀 11 | D2 — CMOS data output bit 2 |
| 핀 12 | D3 — CMOS data output bit 3 |
| 핀 13 | D4 — CMOS data output bit 4 |
| 핀 14 | D5 — CMOS data output bit 5 |
| 핀 15 | D6 — CMOS data output bit 6 |
| 핀 16 | D7 — CMOS data output bit 7 |
| 핀 17 | D8 — CMOS data output bit 8 |
| 핀 18 | D9 — CMOS data output bit 9 |
| 핀 19 | D10 — CMOS data output bit 10 |
| 핀 20 | D11 — CMOS data output bit 11 |
| 핀 21 | D12 — CMOS data output bit 12 |
| 핀 22 | D13 — CMOS data output bit 13 |
| 핀 23 | D14 — CMOS data output bit 14 |
| 핀 24 | D15 — CMOS data output bit 15 (MSB) |
| 핀 25 | DGND — Digital ground |
| 핀 26 | OVDD — Digital output supply |
| 핀 27 | CLKOUT — Clock output (for FPGA synchronization) |
| 핀 28 | NC — Not connected |
| 핀 29 | CLK+ — Encode clock input positive |
| 핀 30 | CLK- — Encode clock input negative |
| 핀 31 | NC — Not connected |
| 핀 32 | OGND — Output driver ground |
| 핀 33 | OVDD — Output driver supply |
| 핀 34 | DITH — Dither control input |
| 핀 35 | MODE — Mode control input |
| 핀 36 | OF — Output format / data randomizer |
| 핀 37 | CS — Chip select for serial interface |
| 핀 38 | SCK — Serial clock for register programming |
| 핀 39 | SDI — Serial data input for register programming |
| 핀 40 | SDO — Serial data output |
| 핀 41 | RESET — ADC reset (active low) |
| 핀 42 | GND — Ground |
| 핀 43 | VAIN — Analog input supply |
| 핀 44 | AVDD — Analog 3.3V supply |
| 핀 45 | GND — Ground |
| 핀 46 | REFP — Reference positive output |
| 핀 47 | REFN — Reference negative output |
| 핀 48 | EPAD — Exposed die pad - must be soldered to ground for thermal dissipation |
일반적인 애플리케이션
LTC2206IUK 적합 용도: 7 애플리케이션s: Cellular Base Station IF Digitisation, Software Defined Radio (SDR) Receiver, Test and Measurement Instrumentation, Radar and Lidar Receiver Front-End, Cable Head-End QAM Demodulator, Medical Ultrasound Imaging Receiver, Spectrum Analyser IF Digitiser.
Cellular Base Station IF Digitisation
The LTC2206IUK digitises the IF stages of 3G/4G/5G base-station receivers, replacing traditional analog demodulation with direct IF-to-digital conversion. Its 80 Msps sample rate comfortably handles 30-45 MHz intermediate frequencies while the 16-bit resolution and 77.5 dB SNR preserve modulation EVM. The 700 MHz input bandwidth supports wideband CDMA/LTE multi-carrier scenarios and the integrated PGA simplifies AGC loops; designers typically place a band-pass SAW filter and an LT6202 driver before the analog input to optimise SFDR.
추천
Software Defined Radio (SDR) Receiver
Software-defined radios benefit from the LTC2206IUK because of its 80 Msps sample rate, 700 MHz input frequency support, and 16-bit dynamic range, allowing direct sampling of HF and lower VHF bands. Designers typically pair the ADC with an FPGA (such as a Xilinx Spartan-6) that performs decimation, channelisation, and demodulation in firmware. The PGA front end maintains the SNR budget as signal strength varies across decades of input range, which is critical for listening to both weak broadcast signals and strong local transmissions on the same antenna.
추천
Test and Measurement Instrumentation
In oscilloscopes, spectrum analysers, and arbitrary waveform capture instruments, the LTC2206IUK provides the precision front-end needed for accurate signal analysis. The 90 dB SFDR ensures harmonic measurements remain accurate over a 90 dB dynamic range, while the 0.5 ps aperture jitter extends accurate undersampling to the tester's bandwidth limit. The integrated PGA enables designers to switch input ranges in firmware without external attenuators, and the 48-QFN footprint fits standard 4-layer digitiser boards with proper thermal vias.
추천
Radar and Lidar Receiver Front-End
Phased-array radar and pulsed-lidar receivers require ADCs that can capture narrow pulses with high dynamic range, and the LTC2206IUK fits that role at 80 Msps / 16-bit resolution. The 700 MHz input bandwidth enables direct sampling of downconverted IFs in S-band radar, while the high SFDR suppresses false targets from interleaving harmonics. The 48-QFN package survives the wider industrial -40 C to +85 C range demanded by outdoor mounted radar electronics, and the part's low aperture jitter maintains timing accuracy across pulse-coherent accumulations.
추천
Cable Head-End QAM Demodulator
The LTC2206IUK digitises 50-1000 MHz downstream QAM channels in cable head-end equipment, supporting dense channel packing while preserving symbol error rate. Its 80 Msps sample rate captures multiple 6 MHz or 8 MHz channels simultaneously when paired with a digital tuner, and the integrated PGA scales to fit differing channel counts. The 16-bit headroom protects against cable plant noise bursts, and the part's high SFDR keeps adjacent-channel interference below the demodulator's error-correction threshold in dense QAM-256 carriers.
추천
Medical Ultrasound Imaging Receiver
In medical ultrasound imaging systems, the LTC2206IUK captures wideband receive signals at 80 Msps and 16-bit resolution, mapping into tissue depth imaging at frame rates up to 60 Hz. The 700 MHz input bandwidth supports high-frequency transducers, and the integrated PGA provides per-channel gain adjustment before beamforming. The 48-QFN footprint fits compact handheld probes, while the 0.5 ps RMS aperture jitter preserves timing alignment between channels that feed digital beamforming DSPs and reconstruct tissue images with accurate depth and amplitude calibration.
추천
Spectrum Analyser IF Digitiser
High-end spectrum analysers use the LTC2206IUK in the final IF digitiser stage, where 80 Msps at 16-bit enables direct capture of the 70 MHz IF without a third conversion stage. The 90 dB SFDR extends the analyser's displayed dynamic range, and the 700 MHz input bandwidth simplifies analyser front-end designs while the PGA replaces mechanical attenuators in modern digital IFs. The 48-QFN footprint, combined with industrial temperature range, supports portable and rack-mounted test equipment where board density and thermal management are key constraints.
추천
추천 제품 요약
엔지니어링 참조 데이터: LTC2206IUK — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | LTC2207IUK | LTC2206IUK-14 | LTC2205IUK | LTC2206CUK |
|---|---|---|---|---|---|
| Package | 48-QFN (7x7) | 48-QFN (7x7) | 48-QFN (7x7) | 48-QFN (7x7) | 48-QFN (7x7) |
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Sample Rate | 80 Msps | 105 Msps | 80 Msps | 65 Msps | 80 Msps |
| Resolution | 16 bit | 16 bit | 14 bit | 16 bit | 16 bit |
| Operating Temperature Range | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | 0 C to +70 C |
| Compliance Grade | Industrial (I) | Industrial (I) | Industrial (I) | Industrial (I) | Commercial (C) |
| RoHS Status | Compliant | Compliant | Compliant | Compliant | Compliant |
| Pin-to-pin Compatible | Yes (baseline) | Yes (drop-in) | Yes (drop-in) | Yes (drop-in) | Yes (drop-in) |
주요 차별점
- Higher sample rate within identical 48-QFN footprint (vs LTC2205IUK)
- Wider input frequency range than lower-resolution family variant (vs LTC2206IUK-14)
- Industrial temperature range option over commercial variant (vs LTC2206CUK)
- More flexible supply chain compared to non-Linear Technology sources (vs Cross-brand ADC (e.g. Texas Instruments ADS42LB69))
설계 노트
Place analog input traces as a 100-ohm differential pair (for differential signaling) with ground shielding on both sides. Keep digital output traces routed away from the analog input and clock signals. Mount the LT3014 or LT1963 LDO as close to AVDD as possible, with a ferrite bead to filter switching noise from upstream rails.
Estimated: at 80 Msps continuous operation with 3.3 V supply and 50% CMOS toggle load, the LTC2206IUK dissipates approximately 0.9 W. The 48-QFN package has theta_JA of approximately 28 C/W on a 4-layer 2 oz copper board, producing a 25 C junction rise above ambient - well within the -40 C to +85 C industrial range.
Do not route the encode clock CLK+/CLK- over the analog input traces, and keep encode clock jitter below 0.5 ps RMS or SNR will degrade at high input frequencies. The exposed die pad (EPAD) MUST be soldered to a continuous ground plane for thermal dissipation and electrical reference; failure to solder the EPAD may result in catastrophic thermal runaway and degraded AC performance per the LTC2206 family datasheet.
Use separate AVDD and OVDD supplies (or LDO regulators) driven from a common 3.3 V source, with LC filters to attenuate switching noise from digital outputs. Decouple each analog pin with a 100 nF X7R 0402 ceramic capacitor and a bulk 10 uF tantalum or ceramic capacitor within 5 mm of the pin. Place the reference bypass capacitors (1 uF and 100 nF) as close to VREF as possible to maintain datasheet SNR.
규정 준수 정보
RoHS and lead-free status confirmed per DigiKey product listing and the LTC2206 datasheet. REACH and conflict-minerals compliance to be verified on customer inquiry.