LTC3633AIUFD - Dual 3A 20V Sync Buck Regulator | Analog Devices
부품 번호: LTC3633AIUFD ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $14.17 | $14.17 |
| 10 | $12.75 | $127.50 |
| 100 | $11.34 | $1,134.00 |
| 500 | $10.21 | $5,105.00 |
| 1,000 | $9.45 | $9,450.00 |
LTC3633AIUFD 개요
A buck (step-down) switching regulator is a DC-DC converter that uses an energy-storage inductor and synchronous MOSFET switches to produce a lower regulated output voltage from a higher input rail with efficiencies typically above 90 percent. Synchronous buck regulators replace the external Schottky diode with an internal low-side MOSFET, reducing conduction loss and improving thermal performance at high output currents. The buck regulator category sits within the broader hierarchy of switching regulators -> DC-DC converters -> power management ICs -> semiconductor devices.
Key features include 0.6V minimum adjustable output, 95 percent maximum efficiency, 1.2 mA quiescent current in Burst Mode operation, programmable soft-start, internal compensation, and a power-good indicator. Each channel supports output voltages from 0.6V to VIN and integrates high-side and low-side MOSFETs rated for 20V operation. The exposed pad provides low thermal resistance, allowing sustained 3A per channel in space-constrained PCB layouts.
The LTC3633A family is offered in three output-voltage-sense variants: LTC3633A (0.6V to 6V VFB reference), LTC3633A-1 (0.6V to VIN VFB reference), and LTC3633A-2 (programmable fixed output). All variants share the same 28-pin WFQFN exposed-pad package and pinout, making them drop-in compatible for BOM flexibility. The 28-WFQFN package with thermal pad enables high-current dual-rail designs without external heatsinking at moderate duty cycles.
Typical applications include distributed power systems, battery-powered instruments, point-of-load supplies, portable electronics, and FPGA/DSP/microprocessor core and I/O rails. The wide 3.6V to 20V input range suits single-cell to multi-cell lithium-ion packs as well as 5V and 12V industrial bus rails.
When designing with the LTC3633AIUFD, select the inductor based on the chosen switching frequency to maintain ripple within 30 percent of peak-to-peak inductor current, and place input ceramic capacitors as close as possible to the VIN and PGND pins to minimize switching-loop inductance.
This page synthesizes distributor pricing, same-brand drop-in variants, and practical design notes not found in the manufacturer datasheet alone.
드롭인 대체품: LTC3633AIUFD — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: LTC3633AIUFD (동일 폼 팩터 및 풋프린트) — 차이점: Input Voltage Range, MSL Level, Operating Temperature Range, Output Voltage Range, Package.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
LTC3633AIUFD-1#PBF
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
LTC3633AIUFD-2#PBF
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
LTC3633AEUFD#PBF
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
LTC3633AIUFD 최대 정격 & 전기적 특성
| 토폴로지 | Synchronous Buck (Step-Down), Dual Channel |
| 입력 전압 범위 | 3.6 V to 20 V |
| 출력 전압 범위 | 0.6 V to 5.5 V (LTC3633A) / up to VIN (LTC3633A-1) |
| 최대 출력 전류 | 3 A per channel (6 A total) |
| Switching Frequency Range | 500 kHz to 4 MHz (phase-lockable) |
| Quiescent Current (Burst Mode) | 1.2 mA typical |
| Maximum Efficiency | 95 % |
| Feedback Reference Voltage | 0.6 V (LTC3633A) |
| 동작 온도 범위 | -40 °C to +125 °C (junction) |
| 패키지 | 28-WFQFN Exposed Pad (4 mm × 5 mm) |
| 핀 수 | 28 |
| 실장 유형 | Surface Mount |
| 출력 수 | 2 |
| MSL 레벨 | 1 |
| RoHS 상태 | Compliant (#PBF suffix) |
LTC3633AIUFD 핀 구성
| 핀 1 | VIN1 — Channel 1 input supply |
| 핀 2 | VIN1 — Channel 1 input supply (second bond pad) |
| 핀 3 | PGND1 — Channel 1 power ground |
| 핀 4 | PGND1 — Channel 1 power ground (second bond pad) |
| 핀 5 | SW1 — Channel 1 switch node |
| 핀 6 | SW1 — Channel 1 switch node (second bond pad) |
| 핀 7 | BST1 — Channel 1 bootstrap for high-side gate drive |
| 핀 8 | VFB1 — Channel 1 feedback (0.6V ref) |
| 핀 9 | VOUT1 — Channel 1 VOUT sense input |
| 핀 10 | RUN1 — Channel 1 enable (active high) |
| 핀 11 | PGOOD1 — Channel 1 power-good indicator |
| 핀 12 | SS1 — Channel 1 soft-start programming |
| 핀 13 | ITH1 — Channel 1 error amplifier compensation |
| 핀 14 | RT/CLK — Timing resistor / external clock input |
| 핀 15 | PGND — Analog ground |
| 핀 16 | VOUT2 — Channel 2 VOUT sense input |
| 핀 17 | SS2 — Channel 2 soft-start programming |
| 핀 18 | VFB2 — Channel 2 feedback (0.6V ref) |
| 핀 19 | RUN2 — Channel 2 enable (active high) |
| 핀 20 | ITH2 — Channel 2 error amplifier compensation |
| 핀 21 | BST2 — Channel 2 bootstrap for high-side gate drive |
| 핀 22 | SW2 — Channel 2 switch node |
| 핀 23 | SW2 — Channel 2 switch node (second bond pad) |
| 핀 24 | PGND2 — Channel 2 power ground |
| 핀 25 | PGND2 — Channel 2 power ground (second bond pad) |
| 핀 26 | VIN2 — Channel 2 input supply |
| 핀 27 | VIN2 — Channel 2 input supply (second bond pad) |
| 핀 28 | PGOOD2 — Channel 2 power-good indicator |
일반적인 애플리케이션
LTC3633AIUFD 적합 용도: 6 애플리케이션s: Distributed Power Systems, Battery-Powered Instruments, FPGA and DSP Multi-Rail Supplies, Industrial 24V Bus Conversion, Point-of-Load Supplies, Portable Medical Devices.
Distributed Power Systems
The LTC3633AIUFD fits distributed power systems as a point-of-load (POL) converter stepping 12V or 5V intermediate bus voltages down to sub-3V rails for downstream ICs. Its 3.6V to 20V input range accepts common bus voltages while delivering 3A per channel with 95% peak efficiency. The two out-of-phase channels cut input RMS ripple current by up to 50%, allowing smaller and cheaper input bulk capacitors in multi-rail POL designs.
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Battery-Powered Instruments
The LTC3633AIUFD suits battery-powered instruments drawing from 1S to 4S Li-ion packs (3.6V to 16.8V nominal). Its 1.2 mA Burst Mode quiescent current extends standby time on portable test equipment, while the 3A per channel output drives microcontrollers, displays, and analog front-ends. The exposed-pad package sustains 3A continuously without external heatsinks, keeping handheld instruments compact and field-ready.
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FPGA and DSP Multi-Rail Supplies
The LTC3633AIUFD is well-matched to FPGA and DSP power trees that require separate core, I/O, and auxiliary rails. Channel 1 can supply 1.0V to 1.8V core at 3A while channel 2 delivers 2.5V or 3.3V I/O at 3A from a common 5V or 12V input. Programmable soft-start and PGOOD output simplify FPGA sequencing requirements, and the 4 MHz switching frequency supports small inductors for tight board layouts.
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Industrial 24V Bus Conversion
In industrial 24V bus systems the LTC3633AIUFD steps the nominal 24V rail (20V to 28V transient-tolerant) down to 5V and 3.3V logic levels for sensors and controllers. Although its 20V absolute maximum input is below 24V nominal, adding a front-end protection MOSFET or pre-regulator allows operation from 24V industrial rails. Two independent channels replace two single-channel bucks, halving PCB area and BOM cost.
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Point-of-Load Supplies
The LTC3633AIUFD serves as a point-of-load converter in telecom and server boards where 12V intermediate buses feed multiple sub-3V loads. Each channel handles 3A continuously with 95% peak efficiency, minimizing thermal rise on densely populated PCBs. The exposed-pad package achieves low thermal resistance, enabling two 3A rails to coexist with neighboring ICs without forced-air cooling in well-designed layouts.
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Portable Medical Devices
The LTC3633AIUFD supports portable medical devices that need two isolated low-voltage rails from a single Li-ion or multi-cell battery pack. Its low 1.2 mA Burst Mode quiescent current extends patient-monitoring runtime between charges, and the exposed-pad WFQFN package fits compact handheld form factors. The two out-of-phase channels reduce input ripple that could couple into sensitive analog front-ends such as ECG or pulse-oximeter signal chains.
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추천 제품 요약
엔지니어링 참조 데이터: LTC3633AIUFD — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | LTC3633AIUFD-1#PBF | LTC3633AIUFD-2#PBF | LTC3633AEUFD#PBF |
|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 28-WFQFN Exposed Pad (4x5 mm) | 28-WFQFN Exposed Pad (4x5 mm) - same | 28-WFQFN Exposed Pad (4x5 mm) - same | 28-WFQFN Exposed Pad (4x5 mm) - same |
| Input Voltage Range | 3.6 V to 20 V | 3.6 V to 20 V | 3.6 V to 20 V | 3.6 V to 20 V |
| Output Current per Channel | 3 A | 3 A | 3 A | 3 A |
| Feedback Reference | 0.6 V (VOUT 0.6 V to 5.5 V) | 0.6 V (VOUT up to VIN) | Fixed factory-trimmed | 0.6 V (same as this product) |
| Switching Frequency | 500 kHz to 4 MHz | 500 kHz to 4 MHz | 500 kHz to 4 MHz | 500 kHz to 4 MHz |
| Temperature Grade | -40 C to +125 C (A grade) | -40 C to +125 C (A grade) | -40 C to +125 C (A grade) | -40 C to +125 C (E extended) |
| Approx. Unit Price (qty 1) | $14.17 | $13.40 | $13.85 | $14.20 |
주요 차별점
- Only variant with 0.6V to 5.5V feedback range and A-grade temperature (vs LTC3633AIUFD-1#PBF)
- Adjustable output vs factory-trimmed fixed output (vs LTC3633AIUFD-2#PBF)
- Two 180-degree out-of-phase channels reduce input ripple (vs Two single-channel LT8606EDC#TRPBF regulators)
설계 노트
Estimated: at VIN=12V, VOUT=3.3V, 3A per channel, the LTC3633AIUFD dissipates roughly 4W total (2W per channel). The 28-WFQFN exposed-pad package requires at least 1 square inch of copper pour tied to PGND on the top and inner layers to keep junction temperature within the 125C rating. Place input ceramic capacitors (2 x 22 µF X7R minimum) as close as possible to the VIN and PGND bond pads of each channel to minimize switching-loop inductance.
When both channels run at full 3A load simultaneously from a 12V input, total internal dissipation can exceed 4W. The exposed pad must be soldered to a continuous ground plane with thermal vias (0.3 mm pitch, 0.2 mm drill) directly under the pad. Without this, theta_JA rises above 50 C/W and the junction temperature can exceed 125C at 85C ambient - derate output current to 2A per channel in such cases.
Do not exceed the 20V absolute maximum input. The BST-to-SW capacitor must be a low-leakage ceramic (X7R or X5R, 0.1 µF to 0.47 µF) placed within 2 mm of the BST pin - a missing or distant BST cap causes shoot-through failures. The RT/CLK resistor sets switching frequency; selecting a value outside the 500 kHz to 4 MHz range can cause sub-harmonic oscillation in current-mode control. Always sequence RUN pins after the input rail settles.
Keep the SW1 and SW2 traces short and surround them with a continuous ground shield to contain switching noise. Route feedback (VFB1, VFB2) traces away from SW nodes and BST traces; capacitive coupling of SW edges into the feedback path causes jitter and instability. Use a single ground plane partitioned so that PGND returns to the input capacitor ground first, then to the exposed pad via thermal vias.
규정 준수 정보
#PBF suffix indicates lead-free, RoHS-compliant version per Analog Devices part numbering convention.
