TUSB7320RKMR - USB 3.0 2-Port xHCI Host Controller | Texas Instruments
부품 번호: PTUSB7320RKMR ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $10.21 | $10.21 |
| 10 | $9.18 | $91.80 |
| 100 | $7.95 | $795.00 |
| 500 | $6.85 | $3,425.00 |
| 1,000 | $6.1 | $6,100.00 |
PTUSB7320RKMR 개요
A USB 3.0 xHCI host controller is a specialized protocol bridge that lets a host processor running an xHCI-class driver enumerate and manage downstream USB devices at SuperSpeed, High-Speed, Full-Speed, and Low-Speed. Within the broader hierarchy it sits as an interface IC between the PCI Express fabric and the USB device tree, enabling motherboards, docking stations, and embedded platforms to add or expand USB ports without redesigning the core chipset. The TUSB7320 family is positioned above PCIe-to-USB 2.0 controllers and below root-complex integrated host silicon that bundles USB directly into the SoC.
Key features include two USB 3.0 downstream ports operating at 5 Gbps SuperSpeed plus backward compatibility with legacy USB rates, one PCI Express Gen 2 upstream port (x1 lane) running at 5 Gbps, integrated 5V to 3.3V/1.8V/1.2V/0.9V core voltage regulators, and per-port power switching controls. The device supports USB attach/detach protocol, overcurrent detection, and dual-role flexibility via ID-pin and OTG signaling on the upstream port.
Architecturally, the TUSB7320 uses a SerDes-based PHY pair per downstream port for SuperSpeed signaling, a hardened xHCI controller engine for transaction translation, and a PCIe physical layer. The internal regulator block removes the need for most external power rails, simplifying board layout. Reference designs in the TUSB73x0 datasheet family describe PCIe edge connector pinout, USB connector wiring, and recommended decoupling for the internal LDO bank.
Typical applications include PC motherboards, notebook docking stations, industrial PCs, point-of-sale terminals, USB port replicators, and embedded platforms that need two USB 3.0 downstream ports from a standard PCIe x1 slot. The device is also found in test fixtures and breakout boards that expose USB 3.0 traffic for analyzer capture.
When using the TUSB7320RKMR, allocate thermal relief on the exposed pad (EP) and observe the 100 us PCIe reference-clock stable period before deasserting PERST to ensure proper link training. Designers should also follow the inrush current profile on VBUS when enabling ports that may already have devices attached.
This page synthesizes distributor pricing, drop-in alternatives from the TUSB73x0 family and cross-vendor host controllers, and practical design notes not found in the manufacturer datasheet.
드롭인 대체품: PTUSB7320RKMR — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
TUSB7340RKMR
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
TUSB7320RKM
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
TUSB7340RKM
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
TUSB7320RKMRG4
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
PEX8605-A50BC/G
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
PTUSB7320RKMR 사양
| Product Type | USB 3.0 xHCI Host Controller |
| Downstream Ports | 2 x USB 3.0 (SuperSpeed) |
| Upstream Interface | PCI Express Gen 2 x1 (5 Gbps) |
| USB Compliance | xHCI 1.0, USB 3.0, USB 2.0, USB 1.1 |
| Legacy USB Support | Low/Full/High Speed (1.5/12/480 Mbps) |
| Battery Charging Support | USB Battery Charging 1.2 (CDP/DCP) |
| Integrated Voltage Regulators | 5V to 3.3V/1.8V/1.2V/0.9V (internal LDO) |
| 패키지 | 100-WQFN-MR (RKM) 9x9 mm with EP |
| 실장 유형 | Surface Mount |
| 동작 온도 | 0C to +70C (commercial) |
| Reference Clock Requirement | 100 us stable PCIe clock before PERST deassertion |
| Per-Port Power Control | Yes (overcurrent detection) |
| RoHS 상태 | Compliant |
PTUSB7320RKMR 100-wqfn-mr (rkm) 9x9 mm with ep 핀 구성 가이드
PTUSB7320RKMR(100-wqfn-mr (rkm) 9x9 mm with ep 패키지)의 핀 구성입니다. 핀 번호, 기능, 연결 다이어그램은 제조사 데이터시트에 정의되어 있습니다. 정확한 풋프린트와 솔더링 지침은 해당 문서를 참조하십시오.
다음에 대한 상세 핀아웃 데이터 없음: PTUSB7320RKMR.
다음을 참조하십시오: 데이터시트 전체 핀 구성은 다음을 참조하십시오.
일반적인 애플리케이션
PTUSB7320RKMR 적합 용도: 6 애플리케이션s: PC Motherboard USB 3.0 Expansion, Notebook Docking Station, Industrial PC and Panel PCs, Point-of-Sale Terminals, USB Port Replicators and Dongles, Embedded Test and Validation Platforms.
PC Motherboard USB 3.0 Expansion
In desktop motherboards the TUSB7320RKMR adds two USB 3.0 5 Gbps downstream ports via one PCIe x1 slot when the chipset's native USB count is exhausted. Its 100-WQFN-MR footprint and integrated 5V to 0.9V LDOs reduce board area versus discrete PCIe-to-USB bridges. Designers benefit from xHCI 1.0 OS support that loads standard inbox drivers on Windows and Linux, eliminating custom driver stacks. Compared to a USB 3.1 Gen 2 upgrade this part tops out at 5 Gbps per port, so it suits mainstream boards rather than high-throughput NVMe docking.
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Notebook Docking Station
Within docking stations the TUSB7320RKMR exposes two USB 3.0 SuperSpeed downstream ports from the dock's PCIe uplink, giving laptops USB charging and 5 Gbps data without requiring USB-C alternate-mode silicon. Per-port overcurrent detection and USB Battery Charging 1.2 CDP/DCP support let downstream phones charge while data is active. The exposed thermal pad handles the heat from two simultaneous 900 mA charging streams. The same package is reused across the TUSB7340RKMR when docks need four downstream ports, simplifying SKU reuse.
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Industrial PC and Panel PCs
Industrial PCs and panel PCs use the TUSB7320RKMR to expose USB 3.0 ports for machine-vision cameras, barcode scanners, and touchscreens while keeping the host CPU free from USB controller interrupts. Its 0C to +70C commercial temperature grade suits factory-floor enclosures with adequate airflow. The internal regulator bank simplifies EMI compliance by reducing external switching converter count. Reference designs show good IEC 61000-4-2 ESD margins when chassis shielding is combined with the recommended TVS array on downstream ports.
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Point-of-Sale Terminals
POS terminals deploy the TUSB7320RKMR to attach barcode imagers, receipt printers, magnetic-stripe readers, and cash-drawer kickers over two USB 3.0 ports from the mainboard's PCIe bus. USB Battery Charging 1.2 support enables customer-facing USB-A ports to charge phones during checkout. The 100-WQFN-MR 9x9 mm form factor fits within slim all-in-one terminal chassis. Engineers can swap to the TUSB7340RKMR for kiosks needing four peripherals without changing the board outline.
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USB Port Replicators and Dongles
External PCIe-cards and slot brackets that need two USB 3.0 ports often center on the TUSB7320RKMR because the integrated regulators remove the need for auxiliary 3.3V rails. The exposed pad provides thermal headroom for sustained bulk-file transfers across both downstream ports simultaneously. With xHCI 1.0 it shows up on Linux/Mac/Windows without vendor-supplied drivers, which is a key selling point for replicator accessories. The TUSB7340RKMR slots into the same reference design when four ports are required.
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Embedded Test and Validation Platforms
USB protocol analyzers and compliance test beds use the TUSB7320RKMR to emulate a real-world xHCI host when validating SuperSpeed peripherals. The deterministic PCIe Gen 2 upstream combined with two controlled downstream ports lets engineers script enumeration stress and link-training tests. The exposed thermal pad keeps the part cool under continuous traffic generator loads, and the USB Battery Charging 1.2 modes can be exercised in CDP/DCP test sequences. The same PCB can be reworked to a TUSB7340RKMR to upgrade test capacity.
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추천 제품 요약
엔지니어링 참조 데이터: PTUSB7320RKMR — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | TUSB7340RKMR | TUSB7320RKM | TUSB7340RKM | TUSB7320RKMRG4 | PEX8605-A50BC/G |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Broadcom |
| Package | 100-WQFN-MR (RKM) 9x9 mm | 100-WQFN-MR (RKM) 9x9 mm - same | 100-WQFN-MR (RKM) 9x9 mm - same | 100-WQFN-MR (RKM) 9x9 mm - same | 100-WQFN-MR (RKM) 9x9 mm - same | 100-WQFN-MR (RKM) 9x9 mm - same |
| Downstream Ports | 2 x USB 3.0 | 4 x USB 3.0 | 2 x USB 3.0 | 4 x USB 3.0 | 2 x USB 3.0 | 0 USB (PCIe switch only) |
| Upstream Interface | PCIe Gen 2 x1 (5 Gbps) | PCIe Gen 2 x1 (5 Gbps) | PCIe Gen 2 x1 (5 Gbps) | PCIe Gen 2 x1 (5 Gbps) | PCIe Gen 2 x1 (5 Gbps) | PCIe Gen 2 x1 (multiple lanes) |
| USB Compliance | xHCI 1.0 | xHCI 1.0 | xHCI 1.0 | xHCI 1.0 | xHCI 1.0 | Not applicable (PCIe switch) |
| Battery Charging 1.2 | Yes (CDP/DCP) | Yes (CDP/DCP) | Yes (CDP/DCP) | Yes (CDP/DCP) | Yes (CDP/DCP) | Not applicable |
주요 차별점
- Integrated multi-rail LDO bank reduces external components (vs TUSB7340RKMR)
- Standard xHCI 1.0 driver support across operating systems (vs PEX8605-A50BC/G)
- Two-port density in a compact 9x9 mm WQFN-100 footprint (vs TUSB7340RKMR)
설계 노트
The TUSB7320RKMR integrates 5V-input LDOs that derive the internal 3.3V, 1.8V, 1.2V, and 0.9V rails, so the PCB typically only requires a single 5V supply at the upstream connector plus a bulk capacitor on VBUS decoupling. Decouple each internal rail pin with a 0.1uF ceramic placed as close as practical to the package per reference designs in the TUSB73x0 datasheet family. For systems that power VBUS from a higher-current source, ensure the upstream 5V rail can support 900 mA per downstream port simultaneously under USB Battery Charging 1.2 conditions plus PCIe inrush.
Route the PCIe upstream differential pair (PETp/n and PERp/n) with 85 ohm differential impedance, length matching better than 5 mil, and no more than two vias total per lane to stay within the Gen 2 eye opening. The USB 3.0 SuperSpeed pairs (SSTXp/n and SSRXp/n) should be 90 ohm differential with reference to a continuous ground plane; avoid crossing these pairs on the same layer as the PCIe lanes. The exposed thermal pad must be soldered to a 9x9 mm copper pour stitched with multiple vias to the inner ground plane for thermal and reference-return integrity.
Deasserting PERST before the 100 MHz PCIe reference clock has been stable for at least 100 us will prevent link training per the TUSB73x0 datasheet - add a reset supervisor or RC delay to enforce this minimum. Hot-plug events where a USB device is already attached when VBUS rises can cause inrush up to the per-port limit; stagger port enable or add soft-start at the connector. Do not assume the WQFN-100 part is hand-rework friendly: reflow profiles per TI MSL specifications must be observed to avoid internal package damage.
규정 준수 정보
RoHS and REACH compliance inferred from Texas Instruments product page language; AEC-Q100 not applicable for commercial PC/embedded interface IC; lead-free and halogen-free specifics to be confirmed against the latest TUSB73x0 datasheet revision. Industrial temperature variants are not offered in this family.
