SI5345A-D10713-GM - 10-Output Jitter Attenuator | Skyworks
부품 번호: SI5345A-D10713-GM ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $34.5 | $34.50 |
| 10 | $31.05 | $310.50 |
| 100 | $25.88 | $2,588.00 |
| 500 | $22.43 | $11,215.00 |
| 1,000 | $19.95 | $19,950.00 |
SI5345A-D10713-GM 개요
An any-frequency jitter attenuator belongs to the clock-tree-on-a-chip product family - a class of timing IC that consolidates multiple frequency synthesis, jitter cleaning, and level translation functions into a single silicon device. Within the broader taxonomy, it sits as clock synthesizer / jitter cleaner > clock generator > timing IC > semiconductor. These parts are the modern successors to legacy XO + PLL designs and are critical wherever a system clock must be regenerated with extremely low phase noise for high-speed serial links, RF data converters, and FPGA/ASIC reference inputs.
Key features include 10 differential or single-ended clock outputs, per-output frequency synthesizers from 1 Hz up to 1028 MHz, an on-chip EEPROM for storing the factory frequency plan, an I2C/SPI control interface, and a digitally programmable jitter-attenuation bandwidth. The Si5345A serves four independent DSPLL lanes from up to two input references, enabling hitless reference switching and holdover when the primary reference is lost. The 64-VFQFN exposed pad (Ravenna-grade thermal pad) supports reflow soldering to a 9 mm x 9 mm PCB land pattern with a thermal resistance consistent with industrial 85 C operation.
Architecturally, the device combines a low-noise fractional-N PLL core, MultiSynth fractional output dividers, and per-output driver strength/slew programming. Skyworks' DSPLL technology allows the loop bandwidth to be tuned from 0.1 Hz to 4 kHz depending on the application's tolerance for input jitter versus wander, letting the designer trade off between tracking and cleaning. This level of programmability - combined with the factory customization suffix - means each '-Dxxxxx-GM' part number represents a complete clock-tree solution that drops into the same PCB footprint as a generic Si5345A blank.
Typical applications include 100G/400G Ethernet line-card reference clocks, OTU/SONET/SDH equipment timing, OTN and PTP grandmaster clocks, broadband wireless infrastructure such as 5G base stations, broadcast video and professional audio systems, and FPGA/ASIC SerDes reference generation. The wide output frequency range up to 1028 MHz covers virtually every common data converter, processor, and transceiver reference in a system.
When laying out the SI5345A-D10713-GM, use a 4-layer PCB with a continuous ground island under the exposed pad; an unbroken thermal pad with multiple stitched vias is required for specified 1 ps period jitter. Decouple each VDD pin with a 0.1 uF X7R placed within 2 mm of the pin, and route each output trace as a 50 ohm (single-ended) or 100 ohm differential transmission line with no stubs. Always configure the device with the ClockBuilder Pro project file matching the ordered part suffix - using a generic Si5345A blank configuration will produce incorrect output frequencies.
드롭인 대체품: SI5345A-D10713-GM — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: SI5345A-D10713-GM (동일 폼 팩터 및 풋프린트) — 차이점: Package, MSL Level, Output Frequency Range, Jitter Attenuation Bandwidth, Operating Temperature Range.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
SI5345A-D-GM
✅ 드롭인✓ 재고 있음
$27.5 / 개
데이터시트 보기 →SI5345A-D10713-GMR
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
SI5345A-D04594-GM
✅ 드롭인✓ 재고 있음
$25.9 / 개
데이터시트 보기 →SI5345A-D04594-GMR
✅ 드롭인✓ 재고 있음
$18.1 / 개
데이터시트 보기 →SI5344B-D-GM
✅ 드롭인✓ 재고 있음
$11.05 / 개
데이터시트 보기 →SI5345A-D10713-GM 사양
| Product Type | Clock Multiplier / Jitter Attenuator |
| 출력 수 | 10 |
| Maximum Output Frequency | 1028 MHz |
| Input Reference Frequency Range | 1 Hz to 750 MHz (per datasheet family) |
| Output Frequency Range | 1 Hz to 1028 MHz |
| Number of Independent DSPLL Lanes | 4 |
| Typical RMS Jitter (12 kHz to 20 MHz) | < 100 fs (Si5345 family typical) |
| Control Interface | I2C / SPI |
| On-Chip EEPROM | Yes (factory programmed with -Dxxxxx frequency plan) |
| Output Types | Differential (LVPECL, LVDS, HCSL, CML) and single-ended CMOS |
| Jitter Attenuation Bandwidth | Digitally programmable, 0.1 Hz to 4 kHz |
| Reference Inputs | Up to 2 references with hitless switching and holdover |
| 패키지 | 64-VFQFN Exposed Pad (9 mm x 9 mm) |
| 동작 온도 범위 | -40C to +85C (industrial grade) |
| 공급 전압 | 3.3 V core, configurable output supply domains |
| Configuration Tool | ClockBuilder Pro |
| RoHS 상태 | Compliant |
| MSL 레벨 | MSL3 / 3 (per JEDEC J-STD-020) |
SI5345A-D10713-GM 64-vfqfn exposed pad (9 mm x 9 mm) 핀 구성 가이드
SI5345A-D10713-GM(64-vfqfn exposed pad (9 mm x 9 mm) 패키지)의 핀 구성입니다. 핀 번호, 기능, 연결 다이어그램은 제조사 데이터시트에 정의되어 있습니다. 정확한 풋프린트와 솔더링 지침은 해당 문서를 참조하십시오.
다음에 대한 상세 핀아웃 데이터 없음: SI5345A-D10713-GM.
다음을 참조하십시오: 데이터시트 전체 핀 구성은 다음을 참조하십시오.
일반적인 애플리케이션
SI5345A-D10713-GM 적합 용도: 7 애플리케이션s: 100G / 400G Ethernet Line-Card Reference Clocking, 5G Base Station Radio Unit Timing, High-Speed ADC and DAC Reference Clock Generation, FPGA and ASIC SerDes Reference Clock Generator, OTU / SONET / SDH Transport Equipment Timing, Broadcast Video and Professional Audio Systems, Industrial Test and Measurement Instrumentation.
100G / 400G Ethernet Line-Card Reference Clocking
The SI5345A-D10713-GM is well suited for 100G and 400G Ethernet line cards where four independent DSPLL lanes must each produce low-jitter reference clocks for the gearbox PHY, the retimer, and the host ASIC SerDes. Its < 100 fs typical RMS jitter over 12 kHz-20 MHz exceeds the IEEE 802.3ba reference-clock jitter mask for 25G/50G PAM4 lanes, removing 802.3bj link-up margin uncertainty. The MultiSynth output dividers deliver up to ten unrelated output frequencies - including 156.25 MHz, 161.13 MHz, and 312.5 MHz - all from a single board-mount device, replacing legacy XO-plus-PLL trees.
추천
5G Base Station Radio Unit Timing
In 5G NR base-station radio units and small cells, the SI5345A-D10713-GM provides hitless reference switching between GNSS-disciplined TCXO and front-haul PTP inputs, while simultaneously synthesizing the 122.88 MHz, 153.6 MHz, and 245.76 MHz reference clocks required by RF data converters, fronthaul eCPRI, and timing-aware FPGAs. The device's 0.1 Hz to 4 kHz digitally programmable jitter-attenuation bandwidth lets the designer optimize loop response for holdover stability over GNSS dropouts. Holdover stability better than 1 ppb for the first hour of free-run operation cleanly satisfies ORAN WG4 synchronization requirements.
추천
High-Speed ADC and DAC Reference Clock Generation
The SI5345A-D10713-GM drives the analog clock inputs of pipelined ADCs and DACs used in digital oscilloscopes, spectrum analyzers, and software-defined-radio front ends where aperture-jitter directly limits signal-to-noise ratio. With sub-100 fs typical output jitter, it minimizes aperture-induced SNR loss for ADC sample rates up to several GS/s, preserving ENOB for frequencies near Nyquist. Ten independent outputs mean a single chip serves a multi-channel oscilloscope front end, replacing multiple crystal oscillators and PLLs with one factory-programmed timing IC.
추천
FPGA and ASIC SerDes Reference Clock Generator
For FPGA and ASIC designs that need multiple GT/GTX/GTY/GTZ/SerDes reference clocks (e.g., 156.25 MHz for 10G, 322.265 MHz for PCIe Gen5, and 312.5 MHz for 100G Ethernet), the SI5345A-D10713-GM's MultiSynth fractional dividers generate non-integer-related frequencies on a single chip. The factory-programmed -D10713 frequency plan can be customized via ClockBuilder Pro and saved to the on-chip EEPROM before board assembly, eliminating firmware reflash at production. The 64-VFQFN package drops onto standard 9 mm x 9 mm footprints, simplifying PCB layout reuse across product variants.
추천
OTU / SONET / SDH Transport Equipment Timing
Telecom transport and OTN equipment must generate multiple telecom-grade clocks including 19.44 MHz for STM-64, 155.52 MHz for OTU1, and 622.08 MHz for OTU2 - all with G.813 Option 1/2 compliance. The SI5345A-D10713-GM's 0.1 Hz to 4 kHz programmable loop bandwidth gives transport designers the freedom to choose between line-side jitter tracking (wide bandwidth) and de-jittering for retiming (narrow bandwidth). Hitless reference switching between primary and secondary clock sources enables carrier-class 0 ms switching.
추천
Broadcast Video and Professional Audio Systems
In SDI video routers, frame-rate converters, and professional audio mixing desks, the SI5345A-D10713-GM provides the 74.25 / 74.25/1.001 MHz UHD-SDI reference clocks plus 48 kHz / 96 kHz / 192 kHz audio word-clock derivatives from a single low-noise source. AES3 / AES67 jitter requirements better than 1 ns UI for HD audio are comfortably satisfied by the < 100 fs RMS jitter. Factor in the 10 outputs, and one timing chip replaces what previously required two or three discrete PLLs in broadcast studio gear.
추천
Industrial Test and Measurement Instrumentation
Bench-top oscilloscopes, signal analyzers, and protocol analyzers rely on a clean, highly flexible clocking core; the SI5345A-D10713-GM provides this with a single 64-VFQFN part. Up to ten user-programmable output frequencies let one board design cover multiple sample-rate / bandwidth SKUs, reducing inventory SKUs and BOM cost. The factory-tuned ClockBuilder Pro plan guarantees the unit arrives at production with the correct reference frequencies loaded, eliminating first-article bring-up friction during instrument calibration.
추천
추천 제품 요약
엔지니어링 참조 데이터: SI5345A-D10713-GM — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | SI5345A-D-GM | SI5345A-D10713-GMR | SI5345A-D04594-GM | SI5345A-D04594-GMR | SI5344B-D-GM |
|---|---|---|---|---|---|---|
| Brand | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions |
| Package | 64-VFQFN Exposed Pad (9x9 mm) | 64-VFQFN Exposed Pad (9x9 mm) - same | 64-VFQFN Exposed Pad (9x9 mm) - same | 64-VFQFN Exposed Pad (9x9 mm) - same | 64-VFQFN Exposed Pad (9x9 mm) - same | 64-VFQFN Exposed Pad (9x9 mm) - same |
| Maximum Output Frequency | 1028 MHz | 1028 MHz | 1028 MHz | 1028 MHz | 1028 MHz | 1028 MHz |
| Number of Outputs | 10 | 10 | 10 | 10 | 10 | 4 (-60% vs 10-output Si5345A) |
| Number of DSPLL Lanes | 4 | 4 | 4 | 4 | 4 | 4 |
| Factory Configuration | Yes (-D10713 plan) | Blank, user-programmable | Yes (-D10713 plan) | Yes (-D04594 plan) | Yes (-D04594 plan) | Blank, user-programmable |
| Packaging Option | Tray (GM) | Tray (GM) | 13-inch Tape & Reel (GMR) | Tray (GM) | 13-inch Tape & Reel (GMR) | Tray (GM) |
| Typical RMS Jitter (12 kHz-20 MHz) | < 100 fs | < 100 fs | < 100 fs | < 100 fs | < 100 fs | < 100 fs |
| Temperature Grade | Industrial -40C to +85C | Industrial -40C to +85C | Industrial -40C to +85C | Industrial -40C to +85C | Industrial -40C to +85C | Industrial -40C to +85C |
주요 차별점
- Factory-pre-programmed frequency plan drops in ready to use (vs SI5345A-D-GM)
- Same silicon in 13-inch tape and reel for high-volume pick-and-place (vs SI5345A-D10713-GMR)
- 10 outputs vs 4 in the Si5344B family (vs SI5344B-D-GM)
설계 노트
The 64-VFQFN exposed-pad package requires a continuous ground island under the thermal pad with a 3x3 to 5x5 array of stitched thermal vias to a lower-layer ground plane. Place 1 x 0.1 uF X7R (or better) decoupling capacitor within 2 mm of every VDD pin to keep the internal sub-regulators quiet. Connect the exposed pad to ground using a flooded keep-out-free region; any split in the ground pour will be visible as elevated phase noise and timing jitter on the outputs.
Route each of the 10 outputs as a 50 ohm single-ended or 100 ohm differential controlled-impedance trace with no stubs; match output trace lengths within the skew budget required by your reference-clock interface (typically 50 mil for 100G Ethernet). Keep the high-speed output traces away from the XO/VCXO input reference traces; minimize cross-talk by stripline-routing the output pairs between ground pours. Place the VCXO as close as possible to the XA/XB input pads to avoid reference jitter pickup.
Do NOT substitute a generic Si5345A-D-GM blank for an installed -D10713 order without first loading the matching ClockBuilder Pro .projx file - the device will output the default frequency plan (typically all 25 MHz) and downstream PHYs will not link. Always confirm the -Dxxxxx suffix matches your ClockBuilder Pro project header before reflow. After PCB assembly, monitor the Si5345A's PLL_LOL pin during bring-up; a sticky locked-light indicates either the wrong project file or a missing XA/XB reference.
Estimated: at maximum output loading (10 outputs into 50 ohms at 1028 MHz, LVPECL), the Si5345A dissipates roughly 1.2 W and the junction-to-ambient thermal resistance of the 64-VFQFN with a 4-layer JEDEC-compliant PCB is on the order of 22 C/W, yielding about 26 C junction temperature rise above 85 C ambient for industrial-rated operation. Adequate thermal vias under the pad keep it within the 125 C maximum junction rating. Forced airflow is not required for the typical 1-1.5 W dissipation in well-designed boards.
Program each output's slew rate through ClockBuilder Pro to match the receiver type: slower 0.5 ns edges for LVPECL, sharper 0.25 ns edges for HCSL receivers, and properly formatted CMOS levels for single-ended loads. Use ClockBuilder Pro's phase-noise simulator to project output jitter BEFORE committing to BOM cost; sometimes tightening the loop bandwidth from 1 kHz to 200 Hz halves jitter at the cost of slightly slower input reference tracking. Verify holdover behavior with the test plans in the Si5345/44/42 family reference manual before shipping production units.
규정 준수 정보
RoHS and lead-free per Skyworks product page; halogen-free status not stated in the provided web data. AEC-Q100 not applicable - industrial-grade timing IC, not automotive.
