SN74AUP1G04DCKR - Low-Power Single Inverter | TI
부품 번호: SN74AUP1G04DCKR ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $0.42 | $0.42 |
| 10 | $0.34 | $3.40 |
| 100 | $0.22 | $22.00 |
| 500 | $0.16 | $80.00 |
| 1,000 | $0.12 | $120.00 |
| 3,000 | $0.09 | $270.00 |
SN74AUP1G04DCKR 개요
An inverter gate is a single-input logic gate whose output is the logical complement of its input; it belongs to the broader category of logic gates within the digital IC hierarchy (logic gate -> combinational logic -> digital IC -> semiconductor). The AUP family is engineered specifically for battery-powered portable equipment where quiescent current draw and dynamic power consumption dominate battery life, making the SN74AUP1G04 well suited for applications that must remain powered continuously.
Key features include a maximum quiescent current (ICC) of 0.9 µA, a typical dynamic power capacitance (Cpd) of 4.1 pF at 3.3 V, low input capacitance of 1.5 pF typical, and Schmitt-trigger action that keeps output noise (overshoot/undershoot) below 10 percent of VCC. Ioff circuitry supports partial-power-down by preventing damaging backflow current when the device is unpowered. The SC-70-5 footprint occupies approximately 2.0 mm x 1.25 mm on the PCB, supporting the densest of portable layouts.
Internally, the SN74AUP1G04 uses a CMOS silicon-gate implementation that delivers rail-to-rail input and output swing, nanoStar and nanoFree package options, and an output drive of ±4 mA at 3.3 V. Typical propagation delay is around 4 ns at 3.3 V with a 30 pF load, which is fast enough for moderate-speed control and general-purpose logic glue but not optimized for high-speed buses.
Typical applications include battery-powered portable medical devices, wearable fitness monitors, hand-held consumer electronics, ultra-low-power IoT sensor nodes, signal conditioning in microcontroller I/O expansion, and level translation between low-voltage MCU domains and 3.3 V peripherals. Designers use the SN74AUP1G04 wherever a single complementary logic signal is needed alongside an ultra-low-power MCU.
When designing with this device, observe the recommended decoupling capacitor (0.1 µF ceramic) placed as close as possible to the VCC pin to control supply-induced jitter, and respect the absolute maximum VCC of 4.6 V to avoid latch-up. For partial-power-down rails, the Ioff feature removes the need for external protection diodes.
This page synthesizes distributor pricing, same-brand and cross-brand drop-in alternatives from the AUP logic family, and practical design notes not found in the manufacturer datasheet alone. Pricing references are stated as of 2026-10-10.
드롭인 대체품: SN74AUP1G04DCKR — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: SN74AUP1G04DCKR (동일 폼 팩터 및 풋프린트) — 차이점: Logic Family, Logic Type, Operating Temperature, Output Type, Package.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
SN74AUP1G04DCKT
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
SN74AUP1G04DCK3
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
SN74AUP1G04DCKR-Q1
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
SN74AUP1G04DRYR
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
SN74AUC1G04DCKR
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
SN74AUP1G04DCKR 최대 정격 & 전기적 특성
| Logic Type | Single Inverter Gate (Y = /A) |
| Number of Channels | 1 |
| Logic Family | 74AUP (AUP - Advanced Ultra-Low-Power) |
| Supply Voltage (VCC) | 0.8 V to 3.6 V |
| Absolute Maximum VCC | 4.6 V |
| Quiescent Current (ICC max) | 0.9 µA |
| Dynamic Power Capacitance (Cpd typ at 3.3 V) | 4.1 pF |
| Input Capacitance (typ) | 1.5 pF |
| Output Drive (at 3.3 V) | ±4 mA |
| Propagation Delay (typ at 3.3 V, 30 pF) | 5.4 ns |
| 출력 유형 | CMOS, Push-Pull |
| Ioff (Partial-Power-Down) | Supported |
| Overshoot/Undershoot | < 10% of VCC |
| 동작 온도 | -40 °C to +85 °C |
| Schmitt-Trigger Input | Yes |
| 패키지 | SC-70-5 (DCK), 2.0 mm x 1.25 mm |
| 실장 유형 | Surface Mount |
| MSL 레벨 | 1 (per JEDEC J-STD-020, 260 °C) |
| RoHS 상태 | Compliant |
| Output Current | ±4 mA |
SN74AUP1G04DCKR 핀 구성
| 핀 1 | NC — Not connected (per datasheet) |
| 핀 2 | A — Logic input (Y = /A) |
| 핀 3 | GND — Ground reference |
| 핀 4 | Y — Inverted logic output |
| 핀 5 | VCC — Supply voltage (0.8 V to 3.6 V) |
일반적인 애플리케이션
SN74AUP1G04DCKR 적합 용도: 6 애플리케이션s: Battery-Powered Wearable Health Monitor, Low-Power IoT Sensor Node, Handheld Test and Measurement Probe, Ultra-Low-Power MCU I/O Conditioning, Industrial Push-Button and Signal Inversion, Consumer Audio Accessory Logic.
Battery-Powered Wearable Health Monitor
The SN74AUP1G04DCKR is a strong fit for battery-powered wearable health monitors because its 0.9 µA maximum quiescent current keeps standby drain negligible and the 0.8 V minimum VCC supports operation directly from near-depleted single-cell chemistries. Its 5.4 ns propagation delay at 3.3 V is sufficient to invert push-button wake signals and to provide logic-level inversion between a low-power MCU GPIO and an AFE chip. The SC-70-5 footprint occupies only ~2.5 mm² of board real estate, an important consideration in wrist-worn form factors. Additionally, the integrated Ioff feature allows the device to be tied to a partial-power-down rail without external protection diodes.
추천
Low-Power IoT Sensor Node
In low-power IoT sensor nodes, the SN74AUP1G04DCKR is typically used as a logic-level inverter between a sensor output and a low-power MCU interrupt or wake-up pin. Its 4.1 pF typical dynamic power capacitance at 3.3 V minimizes switching losses on energy-budgeted nodes, and its Schmitt-trigger input rejects noise picked up on long sensor traces, preventing false wake events. The wide 0.8 V to 3.6 V VCC range is compatible with primary-cell chemistries (Li-MnO2, Li-SOCl2) and with battery-backed supercapacitor energy storage. Designers pair it with sub-gHz transceivers to provide signal inversion in the RF front-end control path.
추천
Handheld Test and Measurement Probe
For handheld test and measurement probes, the SN74AUP1G04DCKR offers the SC-70-5 footprint designers need for pencil-style probe PCBs and the low noise signature required around sensitive analog front ends. Per the TI datasheet, the AUP family exhibits output overshoot and undershoot below 10 percent of VCC, reducing the risk of false triggering in adjacent measurement channels. Its Ioff feature makes it safe to use near probe-tip multiplexing FETs that may be left powered while the rest of the probe is off. Typical uses include input-signal inversion, trigger-signal polarity selection, and output-enable logic.
추천
Ultra-Low-Power MCU I/O Conditioning
The SN74AUP1G04DCKR is commonly used to condition GPIO signals around ultra-low-power MCUs, particularly where the MCU lacks an internal inverter or where the user wants to avoid firmware polling for inverted logic. The Schmitt-trigger input cleans up slowly rising signals from sensor comparators or RC power-on-reset networks, while the push-pull CMOS output drives ±4 mA at 3.3 V into downstream peripherals or level shifters. With 0.9 µA quiescent current and 4.1 pF Cpd, the addition of this gate does not measurably impact energy budgets in sleep-dominated designs. The SC-70-5 footprint is small enough to fit on the back of any breakout board.
추천
Industrial Push-Button and Signal Inversion
In industrial control panels, the SN74AUP1G04DCKR is used for debounced inversion of push-button inputs and for generating complementary drive signals to optocouplers and relays. The Schmitt-trigger input rejects switch-contact bounce for 10-50 ms without external RC components, while the CMOS push-pull output drives optocoupler LEDs directly at 4 mA. The -40 °C to +85 °C industrial temperature range covers most factory environments, and the SC-70-5 package withstands standard SMT assembly profiles to 260 °C per JEDEC J-STD-020. For harsher environments, the AEC-Q100-qualified SN74AUP1G04DCKR-Q1 variant is recommended.
추천
Consumer Audio Accessory Logic
The SN74AUP1G04DCKR serves consumer audio accessories that require inverted logic-level signals, such as headset mute buttons, microphone-active indicators, and inline remote-control protocols. Its 0.9 µA maximum quiescent current extends the operating time of coin-cell-powered accessories, and the SC-70-5 footprint fits inside inline remote enclosures. The Schmitt-trigger input is particularly valuable for cleaning up the slow rise times of mechanical switches in inline remotes, preventing audible glitches in the audio stream. Engineers often use the AUP inverter in combination with I2C-controlled audio codecs to implement mute/microphone bias logic.
추천
추천 제품 요약
엔지니어링 참조 데이터: SN74AUP1G04DCKR — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | SN74AUP1G04DCKT | SN74AUP1G04DCKR-Q1 | SN74AUP1G04DRYR | SN74AUC1G04DCKR |
|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | SC-70-5 (DCK) | SC-70-5 (DCK) - same | SC-70-5 (DCK) - same | X2SON-6 (DRY) - different footprint | SC-70-5 (DCK) - same |
| Logic Family | 74AUP (Ultra-Low-Power) | 74AUP | 74AUP | 74AUP | 74AUC (Advanced Ultra-Low-Voltage) |
| Supply Voltage Range | 0.8 V to 3.6 V | 0.8 V to 3.6 V | 0.8 V to 3.6 V | 0.8 V to 3.6 V | 0.8 V to 2.7 V |
| Maximum Quiescent Current | 0.9 µA | 0.9 µA | 0.9 µA | 0.9 µA | 10 µA (faster, higher) |
| Propagation Delay (typ at 3.3 V) | 5.4 ns | 5.4 ns | 5.4 ns | 5.4 ns | 1.8 ns (faster) |
| AEC-Q100 Qualified | No (industrial only) | No | Yes | No | No |
| Operating Temperature | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +125 °C | -40 °C to +85 °C | -40 °C to +85 °C |
주요 차별점
- Lowest quiescent current in the 74AUP1G04 SC-70 family (vs SN74AUC1G04DCKR)
- Automotive-grade option shares the same footprint (vs SN74AUP1G04DCKR (industrial))
- Lower minimum VCC than competing LVC family (vs SN74LVC1G04 family)
설계 노트
Place a 0.1 µF X5R or X7R ceramic decoupling capacitor as close as possible to the VCC pin (within 1-2 mm) and tie its ground return directly to the GND pin with a short, wide trace. Per the TI datasheet, the AUP family has very low ICC (0.9 µA max) but its dynamic supply current during switching can reach several mA at high toggle rates, so adequate decoupling is essential to prevent logic-level noise on shared rails. For battery-powered designs, consider a ferrite bead in series with VCC if multiple AUP gates share a rail with an RF or sensor analog block.
Route the Y output trace away from sensitive analog inputs; even though the SC-70-5 footprint is small, the SC-70 lead frame can radiate modest switching transients above 50 MHz on the output edge. Use a ground guard trace or via-fence if the output is near an antenna or sensor. For long output traces (>50 mm), add a 33 Ω series resistor at the source end to dampen reflections; this does not interfere with the AUP family drive strength of ±4 mA at 3.3 V. Keep input traces short to leverage the Schmitt-trigger input hysteresis window.
Do not apply voltages above 4.6 V to VCC or any input/output pin, even when VCC is at 0 V; the Ioff feature limits backflow but does not make the device hot-swappable at full system voltage. Estimated: the absolute maximum input clamp current per the JEDEC-style test in the TI datasheet is 50 mA, but in practice continuous input currents should stay below 20 mA to avoid cumulative reliability degradation. Avoid using the part in a non-Schmitt input mode by relying on a slow analog RC rise; the Schmitt-trigger action is built into the AUP gate and cannot be bypassed, so RC rise times below 1 µs are recommended.
규정 준수 정보
RoHS and REACH compliance confirmed per TI product page. Industrial grade only (-40 °C to +85 °C); see SN74AUP1G04DCKR-Q1 for AEC-Q100 automotive qualification. Halogen-free per JEDEC JS709. MSL Level 1 per J-STD-020, unlimited floor life at ≤30 °C / 85 % RH.
