5M570ZT144A5N vs 5M1270ZT144C5N Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci 5M570ZT144A5N disebabkan oleh Intel dan 5M1270ZT144C5N disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Altera
5M1270ZT144C5N - MAX V CPLD 980 Macrocells 114 I/O TQFP-144 | Intel / Altera
5M1270ZT144C5N ✓ AktifPengandingan Spesifikasi
| Parametr | 5M570ZT144A5N | 5M1270ZT144C5N |
|---|---|---|
| Merek | Intel | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Aktif | Aktif |
| Family | MAX V | — |
| Series | 5M570Z | MAX V |
| Macrocells | 440 | 980 |
| User I/Os | 114 | 114 |
| Logic Array Blocks (LABs) | 44 | — |
| User Flash Memory (UFM) | 8 Kbits | 8 Kbits |
| Core Voltage (VCCINT) | 1.71 V to 1.89 V | — |
| I/O Voltage (VCCIO) | 1.2 V / 1.5 V / 1.8 V / 2.5 V / 3.0 V / 3.3 V | — |
| Propagation Delay (tPD) | 17.7 ns | — |
| Maximum User Frequency | [DATA_NEEDED: maximum fMAX] | — |
| Configuration Technology | Non-volatile Flash | — |
| JTAG Support | IEEE 1149.1 Boundary-Scan | — |
| In-System Programmability | Yes (via JTAG) | — |
| Standby Current (typical) | 27 µA | — |
| Suhu Operasi | -40 °C to +125 °C (industrial) | 0 C to +85 C (commercial grade) |
| Kemasan | TQFP-144 (T144), 0.5 mm pitch, 20 mm × 20 mm | TQFP-144 (22 x 22 mm, 0.5 mm pitch) |
| Process Technology | CMOS | — |
| Jenis Pemasangan | Surface Mount | Surface Mount |
| Lead Free / RoHS | Yes (RoHS compliant, -N suffix) | — |
| Moisture Sensitivity Level | MSL 3 | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Elements | — | 1270 |
| Maximum Internal Frequency | — | 118.3 MHz |
| Pin-to-Pin Propagation Delay (tPD) | — | 6.2 ns |
| Internal Frequency (typical) | — | 201 MHz |
| Configuration Memory | — | Flash (non-volatile, in-system programmable) |
| VCCINT (Core Supply) | — | 1.71 V to 1.89 V |
| VCCIO (I/O Supply, per bank) | — | 1.2 V to 3.3 V |
| Number of I/O Banks | — | 4 |
| Supported I/O Standards | — | LVCMOS, LVTTL, PCI up to 3.3 V, 1.2 V to 3.3 V LVCMOS on JTAG pins |
| JTAG Interface | — | IEEE 1149.1 (TMS, TDI, TDO, TCK in Bank 1) |
| Programming Interface | — | JTAG in-system programmable (Altera Quartus II) |
| Program/Erase Cycles | — | Up to 100,000 |
| Status RoHS | — | Compliant |