EP1810GC-35AB vs EP1810JC-45 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP1810GC-35AB disebabkan oleh Altera dan EP1810JC-45 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EP1810GC-35AB | EP1810JC-45 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | NRND |
| Product Family | Classic EPLD | — |
| Technology | CMOS EPROM | CMOS, UV-erasable |
| Number of Macrocells | 48 | — |
| Number of Usable Gates | 1200 | — |
| Maximum Inputs | 64 | — |
| Maximum Outputs | 48 | — |
| Number of I/O Pins | 48 | — |
| Dedicated Input Pins | 12 | — |
| Propagation Delay (tPD) | 35 ns | — |
| Maximum Toggle Frequency | 62.5 MHz | — |
| Supply Voltage (VCC) | 5 V | — |
| Package Type | Pin Grid Array (PGA), ceramic | — |
| Suhu Operasi | [DATA_NEEDED: operating temperature range] | — |
| Programming Method | UV-erasable EPROM, in-system via JTAG-like interface | — |
| Status RoHS | unknown | [DATA_NEEDED: RoHS compliance not stated in verified data] |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Family | — | EP1810 (Classic EPLD Family) |
| Macrocells | — | 48 |
| Equivalent Gates | — | 2100 gates |
| Dedicated Inputs | — | 12 |
| I/O Pins | — | 48 |
| Total User I/O | — | 60 |
| Propagation Delay (tpd) | — | 45 ns |
| Frekuensi Klock Maksimum | — | 33.3 MHz |
| Maximum Supply Voltage | — | 5.25 V |
| Kemasan | — | PLCC-68 (QCCJ, J-Lead, windowed ceramic) |
| Kiraan Pin | — | 68 |
| Package Code | — | QCCJ |
| Temperature Grade | — | Commercial |
| Jenis Pemasangan | — | Surface Mount |