EP1810JC-35 vs EP1810GM883B Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EP1810JC-35 disebabkan oleh Intel dan EP1810GM883B disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EP1810JC-35 EP1810GM883B
Merek Intel Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete NRND
Device Family Classic EPLD (EP1810) EP1810 (Classic EPLD)
Device Type UV-Erasable Complex PLD (UV PLD / CPLD) —
Number of Macrocells 48 —
Propagation Delay (tpd) 35 ns (max) —
Frekuensi Klock Maksimum [DATA_NEEDED: fmax for this speed grade] —
Process Technology CMOS —
Supply Voltage (Vcc) 5 V (nominal) —
Maximum Supply Voltage 5.25 V (per distributor listing) —
Package Type CQCC-68 (Ceramic J-Lead Chip Carrier, QCCJ) Ceramic Pin Grid Array (PGA), 84 pins
Number of Terminals 68 —
Terminal Form J-Bend —
Gambaran Suhu Operasi 0°C to 70°C (Commercial) —
Temperature Grade Commercial —
Erasure Method UV (quartz-windowed ceramic package) —
Status RoHS Compliant (per Altera listing) —
Lead-Free Status Lead-free (per distributor listing) —
Jenis Pemasangan Surface Mount (J-Lead) Through-hole (PGA socket or PCB through-hole)
Logic Architecture Programmable AND/OR array with macrocell outputs —
Macrocells — 48
User Flip-Flops — Up to 64
Total Inputs — 60
Dedicated Inputs — 12
I/O Pins — 48 (bidirectional, tri-state)
Propagation Delay (tPD) — 50 ns max
Supply Voltage (VCC) — 4.5 V to 5.5 V
Technology — CMOS, UV-erasable
Suhu Operasi — -55 °C to +125 °C (Military, MIL-STD-883B)
Package Designator — GM (ceramic PGA)
Processing Level — MIL-STD-883B (Class B)
Programming Method — UV-erasable / Altera programming hardware
Lead-Free / RoHS — [DATA_NEEDED: lead-free status]
Logic Family — TTL-compatible I/O

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