EP1810JC-35 vs EP1810GM883B Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1810JC-35 sa pamamagitan ng Intel at EP1810GM883B sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1810JC-35 | EP1810GM883B |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Device Family | Classic EPLD (EP1810) | EP1810 (Classic EPLD) |
| Device Type | UV-Erasable Complex PLD (UV PLD / CPLD) | — |
| Number of Macrocells | 48 | — |
| Propagation Delay (tpd) | 35 ns (max) | — |
| Maksimum na Taktiko ng Oras | [DATA_NEEDED: fmax for this speed grade] | — |
| Process Technology | CMOS | — |
| Supply Voltage (Vcc) | 5 V (nominal) | — |
| Maximum Supply Voltage | 5.25 V (per distributor listing) | — |
| Package Type | CQCC-68 (Ceramic J-Lead Chip Carrier, QCCJ) | Ceramic Pin Grid Array (PGA), 84 pins |
| Number of Terminals | 68 | — |
| Terminal Form | J-Bend | — |
| Hanay ng Temperature na Operasyon | 0°C to 70°C (Commercial) | — |
| Temperature Grade | Commercial | — |
| Erasure Method | UV (quartz-windowed ceramic package) | — |
| Tindminan RoHS | Compliant (per Altera listing) | — |
| Lead-Free Status | Lead-free (per distributor listing) | — |
| Uri ng Pagpapasok | Surface Mount (J-Lead) | Through-hole (PGA socket or PCB through-hole) |
| Logic Architecture | Programmable AND/OR array with macrocell outputs | — |
| Macrocells | — | 48 |
| User Flip-Flops | — | Up to 64 |
| Total Inputs | — | 60 |
| Dedicated Inputs | — | 12 |
| I/O Pins | — | 48 (bidirectional, tri-state) |
| Propagation Delay (tPD) | — | 50 ns max |
| Supply Voltage (VCC) | — | 4.5 V to 5.5 V |
| Technology | — | CMOS, UV-erasable |
| Temperature na Operasyon | — | -55 °C to +125 °C (Military, MIL-STD-883B) |
| Package Designator | — | GM (ceramic PGA) |
| Processing Level | — | MIL-STD-883B (Class B) |
| Programming Method | — | UV-erasable / Altera programming hardware |
| Lead-Free / RoHS | — | [DATA_NEEDED: lead-free status] |
| Logic Family | — | TTL-compatible I/O |