EP1810JC-45 vs EP1810LC-35 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EP1810JC-45 disebabkan oleh Altera dan EP1810LC-35 disebabkan oleh Rochester Electronics. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Rochester Electronics
EP1810LC-35 EP1810LC-35 - 48-Macrocell Classic EPLD, 35ns, PLCC-68 | Rochester/Altera

EP1810LC-35 - 48-Macrocell Classic EPLD, 35ns, PLCC-68 | Rochester/Altera

EP1810LC-35 ⚠ Bahagian terakhir untuk beli

Pengandingan Spesifikasi

Parametr EP1810JC-45 EP1810LC-35
Merek Altera Rochester Electronics
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup NRND Masa Terakhir Dibeli
Product Type Classic EPLD (Erasable Programmable Logic Device) —
Family EP1810 (Classic EPLD Family) —
Macrocells 48 48
Equivalent Gates 2100 gates 900 usable / 2100 equivalent
Dedicated Inputs 12 —
I/O Pins 48 [DATA_NEEDED: I/O count exact]
Total User I/O 60 —
Propagation Delay (tpd) 45 ns 35 ns (max, '-35' speed grade)
Frekuensi Klock Maksimum 33.3 MHz —
Technology CMOS, UV-erasable CMOS, UV-erasable EPROM
Maximum Supply Voltage 5.25 V —
Kemasan PLCC-68 (QCCJ, J-Lead, windowed ceramic) 68-pin PLCC (J-Lead)
Kiraan Pin 68 —
Package Code QCCJ —
Temperature Grade Commercial —
Jenis Pemasangan Surface Mount Surface Mount (socketable)
Status RoHS [DATA_NEEDED: RoHS compliance not stated in verified data] [DATA_NEEDED]
Device Type — EPLD (Erasable Programmable Logic Device)
Series — Classic EP1810
Maximum Operating Frequency — 28.6 MHz
Supply Voltage (VCC) — 5 V (4.75 V to 5.25 V)
Suhu Operasi — 0C to +70C (commercial)
Configuration Method — UV-erase + EPROM programmer
Programmable Interconnect — Centralized Programmable Interconnect Array (PIA)
Development Tool (legacy) — MAX+PLUS II / A+PLUS
Lead-Free — [DATA_NEEDED]

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