EP1810LC-20T vs EP1810LC-25 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP1810LC-20T disebabkan oleh Intel dan EP1810LC-25 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EP1810LC-20T | EP1810LC-25 |
|---|---|---|
| Merek | Intel | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Family | Altera Classic EPLD | — |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Usable Gates | 900 gates | — |
| Macrocells | 48 | 48 |
| Logic Array Blocks (LABs) | 4 x 12 macrocells | — |
| Maximum Toggle Frequency | 50 MHz | — |
| Pin-to-Pin Logic Delay (tPD) | 20 ns | — |
| Supply Voltage (VCC) | 5 V | 5 V (TTL-compatible) |
| Package Type | PLCC-68 (J-lead) | — |
| Jenis Pemasangan | Surface Mount (socket-compatible) | Surface Mount |
| Configuration Memory | On-chip EEPROM (non-volatile) | — |
| Programming Interface | JTAG (IEEE 1149.1) and Altera Master/Slave serial | — |
| Suhu Operasi | 0C to +70C (commercial) | [DATA_NEEDED: temperature grade for LC package] |
| Shipping Format | Tape & Reel ("T" suffix) | — |
| Status RoHS | Non-compliant (legacy 5V PLCC) | [DATA_NEEDED: RoHS compliance not confirmed in legacy datasheet] |
| Product Family | — | Altera Classic EPLD |
| Part Number | — | EP1810LC-25 |
| Propagation Delay (tPD) | — | 25 ns |
| Dedicated Inputs | — | 12 |
| I/O Pins | — | 48 |
| External Clock Inputs | — | 4 |
| Operating Mode | — | Turbo-only (no slow-power mode) |
| Kemasan | — | 68-pin JLCC (J-leaded ceramic chip carrier) |
| Package Code | — | LC = 68-pin JLCC |
| Technology | — | CMOS EPLD (erasable programmable logic device) |
| Programmable Interconnect | — | Global + Local buses |
| Programming Method | — | Altera Classic programmer + MAX+PLUS II legacy flow |
| Status Lingkungan Hidup | — | Obsolete (legacy Altera Classic family) |