EP1810LC-20T vs EP1810LC-25 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP1810LC-20T sa pamamagitan ng Intel at EP1810LC-25 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP1810LC-20T EP1810LC-25
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family Altera Classic EPLD —
Product Type CPLD (Complex Programmable Logic Device) —
Usable Gates 900 gates —
Macrocells 48 48
Logic Array Blocks (LABs) 4 x 12 macrocells —
Maximum Toggle Frequency 50 MHz —
Pin-to-Pin Logic Delay (tPD) 20 ns —
Supply Voltage (VCC) 5 V 5 V (TTL-compatible)
Package Type PLCC-68 (J-lead) —
Uri ng Pagpapasok Surface Mount (socket-compatible) Surface Mount
Configuration Memory On-chip EEPROM (non-volatile) —
Programming Interface JTAG (IEEE 1149.1) and Altera Master/Slave serial —
Temperature na Operasyon 0C to +70C (commercial) [DATA_NEEDED: temperature grade for LC package]
Shipping Format Tape & Reel ("T" suffix) —
Tindminan RoHS Non-compliant (legacy 5V PLCC) [DATA_NEEDED: RoHS compliance not confirmed in legacy datasheet]
Product Family — Altera Classic EPLD
Part Number — EP1810LC-25
Propagation Delay (tPD) — 25 ns
Dedicated Inputs — 12
I/O Pins — 48
External Clock Inputs — 4
Operating Mode — Turbo-only (no slow-power mode)
Packhaging — 68-pin JLCC (J-leaded ceramic chip carrier)
Package Code — LC = 68-pin JLCC
Technology — CMOS EPLD (erasable programmable logic device)
Programmable Interconnect — Global + Local buses
Programming Method — Altera Classic programmer + MAX+PLUS II legacy flow
Katayuan ng Lifecycle — Obsolete (legacy Altera Classic family)

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