EP20K200CF484C9N vs EP20K200CF484I9 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP20K200CF484C9N disebabkan oleh Altera dan EP20K200CF484I9 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EP20K200CF484C9N | EP20K200CF484I9 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Family | APEX 20KC | APEX 20KC (APEX 20K with ESB/CAM) |
| Device Type | FPGA (Field-Programmable Gate Array) | — |
| Typical Gates | 200,000 | 200,000 |
| Logic Elements | 8,320 | — |
| Embedded System Block (ESB) Bits | 106,496 | — |
| Maximum User I/O | 376 | 376 |
| Frekuensi Klock Maksimum | 250 MHz | — |
| Process Technology | 0.15 um CMOS | 0.15 um CMOS |
| Core Supply Voltage (VCCINT) | 1.8 V | 1.8 V nominal (1.71 V to 1.89 V) |
| I/O Supply Voltage (VCCIO) | 3.3 V / 2.5 V / 1.8 V / 1.5 V (MultiVolt) | — |
| Kemasan | 484-pin FineLine BGA (FBGA) | 484-ball FineLine BGA (FBGA), 1.00 mm pitch |
| Speed Grade | C9 (250 MHz) | -9 (lowest speed in EP20K200 family) |
| Temperature Grade | Industrial (0C to +85C) | — |
| Jenis Pemasangan | Surface Mount (BGA) | — |
| Configuration Scheme | SRAM-based, supports passive serial/parallel and JTAG | — |
| Aras MSL | 3 (per JEDEC J-STD-020) | — |
| Status RoHS | Compliant | unknown - confirm with supplier (legacy part) |
| Series | — | APEX 20KC |
| Logic Elements (Cells) | — | 8,320 |
| Dedicated Inputs | — | 4 |
| Total Terminals | — | 484 (balls) |
| Operating Temperature Grade | — | Industrial (I) |
| Junction Temperature Range | — | -40 C to +100 C |
| Configuration Method | — | SRAM, JTAG in-system programmable |
| Lifecycle | — | Obsolete - EOL announced by Altera/Intel in 2008 |