EP610DC-25 vs EP610DC-30 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP610DC-25 disebabkan oleh Rochester Electronics dan EP610DC-30 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Rochester Electronics
EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester
EP610DC-25 ✓ Aktif
Pengandingan Spesifikasi
| Parametr | EP610DC-25 | EP610DC-30 |
|---|---|---|
| Merek | Rochester Electronics | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Aktif | NRND |
| Family | Altera Classic EPLD | EP610 (Classic Device Family) |
| Product Type | EPLD (Erasable Programmable Logic Device) | Classic EPLD (Erasable Programmable Logic Device) |
| Macrocells | 16 | 16 |
| Equivalent Gates | 300 | — |
| Maximum Propagation Delay (tPD) | 25 ns | — |
| Pipelined Data Rate | Up to 100 MHz | — |
| Number of I/O Pins | 22 | — |
| Number of Dedicated Inputs | 4 | — |
| Total Pin Count | 24 | — |
| Kemasan | 24-pin CDIP (Ceramic DIP, through-hole) | 24-pin CERDIP (windowed) |
| Jenis Pemasangan | Through Hole | Through-Hole |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | — |
| Suhu Operasi | 0 C to +70 C | Commercial (0C to +70C) |
| Technology | CMOS EPROM (UV-erasable) | CMOS EPROM |
| Programming Method | JEDEC fuse-map / UV-erase | — |
| Speed Grade Suffix | -25 (25 ns tPD) | — |
| Logic Expanders | — | 4 (4 product terms per macrocell) |
| Usable Gates | — | 300 |
| Maximum Pipelined Clock Frequency | — | 100 MHz |
| Propagation Delay (tPD) | — | 30 ns |
| Dedicated Inputs | — | 16 |
| I/O Pins | — | 16 (with output enable) |
| Speed Grade | — | -30 (30 ns tPD) |
| Programmability | — | UV-erasable, windowed EPROM |
| Security Bit | — | Yes (protects design after programming) |
| Output Modes | — | Registered and Combinatorial |