EP910JC-30 vs EP910LC-35 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP910JC-30 disebabkan oleh Intel dan EP910LC-35 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EP910JC-30 | EP910LC-35 |
|---|---|---|
| Merek | Intel | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Family | Classic EPLD (MAX-style) | Classic (EP910) |
| Propagation Delay (tpd) | 30 ns | — |
| Maximum Internal Frequency (Fmax) | 33.3 MHz | — |
| Macrocells | 24 | 24 |
| Inputs | 36 | — |
| Product Terms | 240 | — |
| Outputs | 10 dedicated | — |
| Supply Voltage (Vcc) | 5 V | — |
| Technology | CMOS EPROM, UV-erasable | CMOS EPROM |
| Kemasan | 44-pin Windowed Ceramic J-Lead Chip Carrier (CQCC-44 / JLCC-44) | PLCC-44 (J-lead, LC suffix) |
| Suhu Operasi | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| Supply Current (Icc) | [DATA_NEEDED: Icc typical / maximum] | — |
| Jenis Pemasangan | Surface Mount (socket-mountable) | — |
| Status RoHS | [DATA_NEEDED: RoHS compliance] | Not applicable (legacy product) |
| Logic Blocks | 24 macrocells (AND/OR array architecture) | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | — | 450 |
| Propagation Delay (tPD) | — | 35 ns |
| Maximum Toggle Frequency | — | 28.6 MHz |
| Supply Voltage (VCC) | — | 5 V |
| Kiraan Pin | — | 44 |
| Programmable Flip-Flops | — | Yes (per macrocell) |
| Output Enable Control | — | Per macrocell |
| Erasure Method | — | UV (windowed) or OTP (plastic) |