EP910JC-30 vs EP910LC-35 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910JC-30 sa pamamagitan ng Intel at EP910LC-35 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910JC-30 | EP910LC-35 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | Classic EPLD (MAX-style) | Classic (EP910) |
| Propagation Delay (tpd) | 30 ns | — |
| Maximum Internal Frequency (Fmax) | 33.3 MHz | — |
| Macrocells | 24 | 24 |
| Inputs | 36 | — |
| Product Terms | 240 | — |
| Outputs | 10 dedicated | — |
| Supply Voltage (Vcc) | 5 V | — |
| Technology | CMOS EPROM, UV-erasable | CMOS EPROM |
| Packhaging | 44-pin Windowed Ceramic J-Lead Chip Carrier (CQCC-44 / JLCC-44) | PLCC-44 (J-lead, LC suffix) |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| Supply Current (Icc) | [DATA_NEEDED: Icc typical / maximum] | — |
| Uri ng Pagpapasok | Surface Mount (socket-mountable) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | Not applicable (legacy product) |
| Logic Blocks | 24 macrocells (AND/OR array architecture) | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | — | 450 |
| Propagation Delay (tPD) | — | 35 ns |
| Maximum Toggle Frequency | — | 28.6 MHz |
| Supply Voltage (VCC) | — | 5 V |
| Bilang ng Pin | — | 44 |
| Programmable Flip-Flops | — | Yes (per macrocell) |
| Output Enable Control | — | Per macrocell |
| Erasure Method | — | UV (windowed) or OTP (plastic) |