EP910LC-32 vs EP910LC-35T Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EP910LC-32 disebabkan oleh Altera dan EP910LC-35T disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EP910LC-32 EP910LC-35T
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete NRND
Device Family Altera Classic EPLD —
Number of Macrocells 24 —
Number of Usable Gates 900 gates (typical) —
Number of Dedicated Inputs 10 —
Number of I/O Pins 20 —
Kemasan PLCC-32 PLCC-44 (J-lead)
Speed Grade -32 —
Maximum Toggle Frequency (fMAX) [DATA_NEEDED: fMAX value in MHz for -32 grade] —
Pin-to-Pin Propagation Delay (tPD) [DATA_NEEDED: tPD in ns for -32 grade] —
Supply Voltage (VCC) 5 V 5 V
Logic Family Low-power CMOS (LC suffix) —
Programming Method UV-erasable or one-time programmable (OTP for LC windowless variant) —
Gambaran Suhu Operasi [DATA_NEEDED: commercial or industrial grade] —
I/O Standard TTL-compatible —
Jenis Pemasangan Surface Mount (PLCC socket or direct solder) Surface Mount (PLCC socket or solder)
Status RoHS unknown [DATA_NEEDED: RoHS status not in verified data]
Aras MSL unknown MSL 3 (168 hours)
Family — Classic EPLD (EP910)
Logic Capacity — 450 usable gates
Macrocells — 24
Propagation Delay (tPD) — 35 ns
Maximum Operating Frequency — 28.6 MHz
User I/O Pins — 36
Process Technology — CMOS (EPROM-based)
Suhu Operasi — 0C to +70C (commercial)
Erasure Method — UV-erasable window (ceramic package) / OTP (plastic)
Programming — Altera programming hardware + MAX+PLUS II

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