EP910LC-35 vs EP910DC-35 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP910LC-35 disebabkan oleh Altera dan EP910DC-35 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EP910LC-35 | EP910DC-35 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Classic (EP910) | Classic EPLD EP910 |
| Macrocells | 24 | 24 |
| Usable Gates | 450 | 900 gates |
| Propagation Delay (tPD) | 35 ns | — |
| Maximum Toggle Frequency | 28.6 MHz | — |
| Supply Voltage (VCC) | 5 V | — |
| Technology | CMOS EPROM | CMOS, UV-erasable EPROM cell |
| Kemasan | PLCC-44 (J-lead, LC suffix) | 40-pin CDIP (Ceramic DIP) with quartz window |
| Suhu Operasi | 0C to +70C (commercial) | 0 °C to +70 °C (commercial) |
| Kiraan Pin | 44 | — |
| Programmable Flip-Flops | Yes (per macrocell) | — |
| Output Enable Control | Per macrocell | — |
| Erasure Method | UV (windowed) or OTP (plastic) | — |
| Status RoHS | Not applicable (legacy product) | Non-compliant (ceramic DIP with Pb-bearing lead finish) |
| Device Type | — | UV-Erasable CMOS PLD (PAL-type) |
| Architecture | — | PAL-type sum-of-products AND-OR array |
| Product Terms | — | 240 |
| Dedicated Inputs | — | 12 |
| I/O Pins | — | 24 |
| Total Inputs | — | 36 |
| Propagation Delay (tpd) | — | 35 ns |
| Frekuensi Klock Maksimum | — | 37 MHz (typical, internal) |
| Supply Voltage (Vcc) | — | 4.75 V to 5.25 V (5 V nominal) |
| Lead Pitch | — | 2.540 mm |
| Termination Style | — | Through-Hole |
| Programming Method | — | JEDEC fuse map via device programmer; UV erase |
| Lifecycle | — | Obsolete / last-time-buy from authorized distributors |