EP910PC-25 vs EP910PC-0 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP910PC-25 disebabkan oleh Altera dan EP910PC-0 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EP910PC-25 | EP910PC-0 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Product Family | Classic EPLD | — |
| Usable Gates | 900 | 900 gates |
| Integration Gates (typical) | 4800 | — |
| Macrocells | 24 | 24 |
| Pin-to-Pin Delay (tPD) | 25 ns | — |
| Maximum Operating Frequency (fMAX) | 33.3 MHz | — |
| Supply Voltage (VCC) | 5 V +/- 10% | — |
| Technology | CMOS EPROM | — |
| Kemasan | PDIP-24 (Plastic DIP) | PDIP-40 (Plastic DIP, 40-pin) |
| Kiraan Pin | 24 | — |
| Dedicated Inputs | 10 | 10 |
| Dedicated I/O Pins | 12 | — |
| TTL Compatibility | 100% TTL emulation | — |
| Suhu Operasi | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Erasure Method | Not erasable in plastic package (windowless) | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Family | — | Classic EPLD |
| Logic Blocks | — | 6 (4 macrocells each) |
| I/O Pins | — | 24 |
| Speed Grade | — | -0 (slowest) |
| Tegangan Pemberi Arus | — | 5 V (single supply) |
| Process Technology | — | CMOS |
| Logic Compatibility | — | 100% TTL emulation |
| Programming Method | — | UV-erasable / OTP |
| Jenis Pemasangan | — | Through-Hole (DIP) |