EP910PC-25 vs EP910PC30T Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP910PC-25 disebabkan oleh Altera dan EP910PC30T disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EP910PC-25 | EP910PC30T |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Product Family | Classic EPLD | — |
| Usable Gates | 900 | — |
| Integration Gates (typical) | 4800 | — |
| Macrocells | 24 | — |
| Pin-to-Pin Delay (tPD) | 25 ns | — |
| Maximum Operating Frequency (fMAX) | 33.3 MHz | — |
| Supply Voltage (VCC) | 5 V +/- 10% | 5 V (4.75 V to 5.25 V) |
| Technology | CMOS EPROM | — |
| Kemasan | PDIP-24 (Plastic DIP) | 24-pin PDIP (PC) |
| Kiraan Pin | 24 | 24 |
| Dedicated Inputs | 10 | — |
| Dedicated I/O Pins | 12 | — |
| TTL Compatibility | 100% TTL emulation | — |
| Suhu Operasi | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| Erasure Method | Not erasable in plastic package (windowless) | — |
| Family | — | Altera Classic EPLD |
| Device Series | — | EP910 |
| Number of Macrocells | — | 24 |
| Number of I/O Pins | — | 24 |
| Number of Dedicated Inputs | — | 12 |
| Maximum Product Terms | — | 240 |
| Propagation Delay (tPD) | — | 30 ns |
| Maximum Clock Frequency (fMAX) | — | 33.3 MHz |
| Process Technology | — | CMOS |
| Programmable Logic Architecture | — | PAL-type sum-of-products, EPLD |
| Jenis Pemasangan | — | Through-Hole (THT) |
| Speed Grade | — | -30 (30 ns tPD) |
| Programming Technology | — | EPROM (OTP in plastic package, UV-erasable in windowed package) |
| Status RoHS | — | [DATA_NEEDED: RoHS compliance status] |