EPC4QC100TQ vs EPC4QC1C00N Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EPC4QC100TQ disebabkan oleh Altera dan EPC4QC1C00N disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EPC4QC100TQ EPC4QC1C00N
Merek Altera Altera
Kategori Memory ICs FPGA & CPLD
Status Lingkungan Hidup NRND Obsolete
Jenis Ingatan Flash configuration PROM —
Saiz Ingatan 4 Mbit —
Configuration Modes Passive Serial (PS), JTAG —
Maximum Configuration Clock 66 MHz —
Tegangan Pemberi Arus 3.3 V typical (5.0 V tolerant I/O) —
Antaramuka Serial configuration data, JTAG boundary scan —
Kemasan 100-pin TQFP (TQ) 20x14 mm 100-pin PQFP (QFP-100)
Jenis Pemasangan Surface Mount —
Suhu Operasi -40C to +85C -40 C to +85 C (industrial)
Compression Support Yes (Altera proprietary) —
In-System Programmable Yes —
Compatible FPGA Families Stratix, APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K —
Aras MSL 3 (168 hours) 3 (per JEDEC J-STD-020)
Status RoHS [DATA_NEEDED: RoHS status not in verified data] [DATA_NEEDED: RoHS compliance status]
Lead Free [DATA_NEEDED: lead-free status not in verified data] —
Device Family — Enhanced Configuration Device (EPC4)
Memory Density — 4 Mbit (4,194,304 bits)
Supply Voltage (VCC) — 3.0 V to 3.6 V (3.3 V typical)
I/O Voltage Tolerance — 3.3 V / 5 V tolerant
Interface to FPGA — Serial DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE
Configuration Data Width — 4-bit multiplexed on single DATA pin
In-System Programming — JTAG (IEEE 1149.1)
Programming Voltage — On-chip generated, no external VPP
Page Mode — Yes, multi-page storage supported
Target FPGA Families — Stratix, Cyclone, APEX, Mercury, ACEX
Configuration Clock (DCLK) — [DATA_NEEDED: DCLK max frequency]
Lead-Free — [DATA_NEEDED: lead-free status]

Laporan Datasheet & Sumber

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