EPC8Q100 vs EPC8Q1100 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EPC8Q100 disebabkan oleh Altera dan EPC8Q1100 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Altera
EPC8Q1100 - 8 Mbit Enhanced Config Device for SRAM FPGAs | Altera
EPC8Q1100 ⚠ Bahagian terakhir untuk beliPengandingan Spesifikasi
| Parametr | EPC8Q100 | EPC8Q1100 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Masa Terakhir Dibeli |
| Memory Density | 8 Mbit (8,388,608 bits) | 8 Mbit (8,388,608 bits) |
| Jenis Ingatan | NOR Flash, One-Time-Programmable (OTP) via JTAG | — |
| Configuration Interface | Altera EPC serial (DATA, DCLK, nCS, nINIT_CONF, nSTATUS, DONE) | Altera Enhanced Config serial interface (DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE) |
| Supply Voltage VCC | 5.0 V (3.3 V core generated on-chip) | — |
| Internal Core Voltage | 3.3 V (on-chip LDO) | — |
| Maximum EPC Clock | 33 MHz | — |
| Programmability | In-system via IEEE 1149.1 JTAG | — |
| FPGA Compatibility | APEX 20K, APEX II, Cyclone, Cyclone II, Stratix, Stratix GX | — |
| Configuration Mode Support | FPP, PS, AS, JTAG (FPGA-dependent) | — |
| Program/Erase Endurance | [DATA_NEEDED: cycle count] | — |
| Data Retention | [DATA_NEEDED: minimum years] | [DATA_NEEDED: data retention years] |
| Gambaran Suhu Operasi | 0 C to +70 C (commercial) | — |
| Storage Temperature Range | [DATA_NEEDED: range] | — |
| Kemasan | 100-pin PQFP (20 x 14 mm) | 100-pin PQFP (plastic quad flat pack) |
| Jenis Pemasangan | Surface Mount | — |
| Aras MSL | [DATA_NEEDED: level] | — |
| Lead-Free / RoHS | [DATA_NEEDED: status] | — |
| Product Type | — | Enhanced Configuration Device (boot PROM) |
| Supported FPGAs | — | Altera SRAM-based LUT FPGAs (Cyclone, Stratix, APEX, ACEX, Mercury, Excalibur) |
| Max DCLK Frequency | — | 33 MHz (Fast-mode) |
| Supply Voltage (VCC) | — | 3.0 V to 3.6 V |
| Supply Voltage (VCCIO for FPGA interface) | — | 1.8 V / 2.5 V / 3.3 V tolerant |
| Programming Interface | — | IEEE Std 1149.1 JTAG (ISP) + serial byte-blaster mode |
| In-System Programmable | — | Yes |
| Suhu Operasi | — | -40 C to +85 C (industrial) |
| Operating Current (active read) | — | [DATA_NEEDED: active ICC] |
| Standby Current | — | [DATA_NEEDED: ICC standby] |
| Endurance (program/erase cycles) | — | [DATA_NEEDED: endurance cycles] |
| Status RoHS | — | [DATA_NEEDED: RoHS status] |
| Lead-Free | — | [DATA_NEEDED: lead-free] |