EPM3128ATC100-10N vs EPM3512AQC20810 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM3128ATC100-10N disebabkan oleh Altera dan EPM3512AQC20810 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EPM3128ATC100-10N EPM3512AQC20810
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup NRND Obsolete
Family MAX 3000A MAX 3000A
Product Type CPLD (Complex Programmable Logic Device) —
Macro Cells 128 512
Usable Gates 2500 —
Number of I/O 80 —
Logic Elements / Blocks 8 LABs (16 macrocells each) —
Propagation Delay (tPD) 10 ns 10 ns
Maximum Internal Frequency (fMAX) 98 MHz —
Supply Voltage VCCINT 3.3 V —
I/O Bank Voltage VCCIO 3.3 V or 2.5 V (selectable) —
Configuration Memory CMOS EEPROM (non-volatile, instant-on) On-chip EEPROM, non-volatile, 100+ cycles, 10+ year retention
In-System Programming IEEE Std. 1532-compliant ISP via JTAG —
Kemasan 100-pin TQFP (14 x 14 x 1.0 mm) 208-pin PQFP (PQ208)
Suhu Operasi 0 °C to +70 °C (commercial) —
Jenis Pemasangan Surface Mount —
Status RoHS Compliant [DATA_NEEDED: RoHS status]
Lead-Free Yes —
Aras MSL 3 (per JEDEC J-STD-020) —
Logic Type — CPLD (EEPROM-based, non-volatile)
User I/Os — 172
Logic Array Blocks (LABs) — 16
Usable Gates (equivalent) — 10000
Speed Grade — -10 (tPD = 10 ns)
Maximum Internal Frequency — 132 MHz
Core Supply Voltage (VCCINT) — 3.3 V
I/O Supply Voltage (VCCIO) — 3.3 V
In-System Programmability — Yes (IEEE 1149.1 JTAG, 3.3 V ISP)
PCI Compliance — PCI Local Bus Specification Revision 2.2 compliant
Operating Temperature (commercial) — 0 °C to +70 °C
Process Technology — 0.30 µm CMOS EEPROM

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