EPM3256ATC144-7 vs EPM3256ATC144-7N Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM3256ATC144-7 disebabkan oleh Altera dan EPM3256ATC144-7N disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Altera
EPM3256ATC144-7N - MAX 3000A CPLD 256 Macro 7.5ns | Altera
EPM3256ATC144-7N ⚠ Bahagian terakhir untuk beliPengandingan Spesifikasi
| Parametr | EPM3256ATC144-7 | EPM3256ATC144-7N |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Masa Terakhir Dibeli |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 256 | — |
| User I/Os | 116 | 116 |
| Logic Elements / Gates | 600 to 10,000 usable gates | — |
| Propagation Delay (tPD) | 7.5 ns | 7.5 ns |
| Counter Frequency (fCNT) | 227.3 MHz | — |
| Speed Grade | -7 | — |
| Supply Voltage - Core (VCCINT) | 3.3 V | — |
| Supply Voltage - I/O (VCCIO) | 2.5 V / 3.3 V / 5.0 V | — |
| In-System Programming | IEEE Std. 1532 compliant, 3.3 V ISP | — |
| Kemasan | TQFP-144 (LFQFP, gull-wing) | 144-pin TQFP |
| Suhu Operasi | 0C to +70C (Commercial) | 0C to +70C (Commercial) |
| Kiraan Pin | 144 | — |
| Jenis Pemasangan | Surface Mount | Surface Mount |
| PCI Compliance | PCI Local Bus Specification Revision 2.2 (speed grades -4 to -10) | — |
| JTAG Support | IEEE Std. 1149.1 boundary-scan | IEEE 1149.1 boundary-scan |
| Device Type | — | CPLD - Complex Programmable Logic Device |
| Macro Cells | — | 256 |
| Logic Gates (usable) | — | 5,000 |
| Number of Logic Array Blocks (LABs) | — | 16 |
| Maximum Internal Frequency | — | 126.6 MHz |
| Supply Voltage (VCCIO) | — | 3.0 V to 3.6 V |
| Programmable Logic Technology | — | CMOS EEPROM-based |
| In-System Programmable (ISP) | — | Yes (3.3 V) |
| Logic Family | — | CMOS |
| Status RoHS | — | Compliant |