EPM3256ATC144-7 vs EPM3256ATC144-7N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM3256ATC144-7 sa pamamagitan ng Altera at EPM3256ATC144-7N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM3256ATC144-7 | EPM3256ATC144-7N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Huling Pagbili |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 256 | — |
| User I/Os | 116 | 116 |
| Logic Elements / Gates | 600 to 10,000 usable gates | — |
| Propagation Delay (tPD) | 7.5 ns | 7.5 ns |
| Counter Frequency (fCNT) | 227.3 MHz | — |
| Speed Grade | -7 | — |
| Supply Voltage - Core (VCCINT) | 3.3 V | — |
| Supply Voltage - I/O (VCCIO) | 2.5 V / 3.3 V / 5.0 V | — |
| In-System Programming | IEEE Std. 1532 compliant, 3.3 V ISP | — |
| Packhaging | TQFP-144 (LFQFP, gull-wing) | 144-pin TQFP |
| Temperature na Operasyon | 0C to +70C (Commercial) | 0C to +70C (Commercial) |
| Bilang ng Pin | 144 | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| PCI Compliance | PCI Local Bus Specification Revision 2.2 (speed grades -4 to -10) | — |
| JTAG Support | IEEE Std. 1149.1 boundary-scan | IEEE 1149.1 boundary-scan |
| Device Type | — | CPLD - Complex Programmable Logic Device |
| Macro Cells | — | 256 |
| Logic Gates (usable) | — | 5,000 |
| Number of Logic Array Blocks (LABs) | — | 16 |
| Maximum Internal Frequency | — | 126.6 MHz |
| Supply Voltage (VCCIO) | — | 3.0 V to 3.6 V |
| Programmable Logic Technology | — | CMOS EEPROM-based |
| In-System Programmable (ISP) | — | Yes (3.3 V) |
| Logic Family | — | CMOS |
| Tindminan RoHS | — | Compliant |