EPM3256ATC144-7N vs EPM3256ATI144-10N Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM3256ATC144-7N disebabkan oleh Altera dan EPM3256ATI144-10N disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Altera
EPM3256ATC144-7N - MAX 3000A CPLD 256 Macro 7.5ns | Altera
EPM3256ATC144-7N ⚠ Bahagian terakhir untuk beliPengandingan Spesifikasi
| Parametr | EPM3256ATC144-7N | EPM3256ATI144-10N |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Masa Terakhir Dibeli | Obsolete |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD - Complex Programmable Logic Device | CPLD - Complex Programmable Logic Device |
| Macro Cells | 256 | — |
| Logic Gates (usable) | 5,000 | — |
| Number of Logic Array Blocks (LABs) | 16 | — |
| User I/Os | 116 | 116 |
| Propagation Delay (tPD) | 7.5 ns | 10 ns |
| Maximum Internal Frequency | 126.6 MHz | — |
| Supply Voltage (VCCIO) | 3.0 V to 3.6 V | — |
| Programmable Logic Technology | CMOS EEPROM-based | — |
| In-System Programmable (ISP) | Yes (3.3 V) | — |
| Suhu Operasi | 0C to +70C (Commercial) | -40 C to +85 C (industrial, "I" suffix) |
| Kemasan | 144-pin TQFP | 144-pin TQFP |
| Jenis Pemasangan | Surface Mount | Surface Mount |
| Logic Family | CMOS | — |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| Status RoHS | Compliant | Compliant |
| Macrocells | — | 256 |
| Usable Gates | — | 5,000 |
| Logic Blocks / Logic Elements | — | 16 |
| Max Frequency (fMAX) | — | 95.2 MHz |
| Supply Voltage - Core | — | 3.3 V |
| I/O Voltage Support | — | 1.8 V / 2.5 V / 3.3 V (multi-voltage) |
| In-System Programmability | — | Yes, IEEE Std. 1532 compliant |
| Boundary-Scan Test (BST) | — | Yes, IEEE Std. 1149.1 (JTAG) |
| Lead-Free / Pb-Free | — | Yes ("N" suffix) |
| Process Technology | — | CMOS EEPROM-based, non-volatile |
| Aras MSL | — | 3 (per JEDEC J-STD-020, typical for TQFP) |