EPM3512AFC256-20 vs EPM3512AFC256-18 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM3512AFC256-20 disebabkan oleh Altera dan EPM3512AFC256-18 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EPM3512AFC256-20 EPM3512AFC256-18
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Family MAX 3000A MAX 3000A
Macrocells 512 512
Typical Usable Gates 10,000 —
Speed Grade -20 (20 ns tPD) —
Kemasan 256-ball FBGA (Fine-pitch BGA) 256-ball FineLine BGA (FCBGA)
Kiraan Pin 256 —
Operating Voltage (VCCINT) 3.3 V (3.0 V to 3.6 V) —
I/O Voltage (VCCIO) 2.5 V or 3.3 V (5.0 V tolerant inputs) —
I/O Standards LVTTL, LVCMOS, 2.5 V, 3.3 V, 5.0 V tolerant —
Program Memory Type EEPROM (non-volatile) —
In-System Programmability Yes (JTAG IEEE 1149.1) —
JTAG Support Yes (boundary-scan + ISP) —
Jenis Pemasangan Surface Mount Surface Mount
Suhu Operasi [DATA_NEEDED: operating temperature range] [DATA_NEEDED: industrial/commercial grade]
Status RoHS [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: not specified in retrieved data]
Aras MSL [DATA_NEEDED: MSL moisture sensitivity level] —
Configuration Memory Internal EEPROM —
Logic Array Blocks (LABs) — 16
Maximum User I/O Pins — 212
Pin-to-Pin Delay (tPD1) — 18 ns
Global Clock Networks — 4
VCCINT (Core Supply) — 3.0 V to 3.6 V (3.3 V typical)
VCCIO (I/O Supply) — 2.5 V or 3.3 V (MultiVolt)
Programming Technology — EEPROM (non-volatile)
In-System Programming — IEEE Std. 1532 / JTAG (IEEE Std. 1149.1)
Ball Pitch — 1.0 mm

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