EPM3512AFC256-5C vs EPM3512AFC256-7N Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM3512AFC256-5C disebabkan oleh Altera dan EPM3512AFC256-7N disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EPM3512AFC256-5C EPM3512AFC256-7N
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) —
Macrocells 512 512
Usable Gates 10,000 10,000
Maximum Operating Frequency 95.2 MHz —
Pin-to-Pin Delay (tPD) 5 ns —
Supply Voltage - Core (VCCINT) 3.3 V —
I/O Voltage (VCCIO) 2.5 V / 3.3 V / 5.0 V (banked MultiVolt I/O) —
User I/O Pins 212 (max) —
Kemasan 256-ball FBGA, 17 mm × 17 mm, 1.0 mm pitch 256-pin FineLine BGA (FBGA-256), 1.0 mm pitch
Suhu Operasi 0 °C to +70 °C (commercial, "C" grade) 0 C to 70 C (commercial)
Programming Interface IEEE Std. 1532 / JTAG (4-wire) in-system programmable JTAG (IEEE 1149.1)
Jenis Pemasangan Surface Mount Surface Mount
Status RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Technology EEPROM-based macrocell, non-volatile —
Product Type — CPLD (Complex Programmable Logic Device)
User I/Os — 208
Logic Blocks — 16 (32 macrocells each)
Propagation Delay (tPD) — 7.5 ns
Maximum Internal Frequency (fMAX) — 116.3 MHz
Core Supply Voltage (VCCINT) — 3.3 V
I/O Supply Voltage (VCCIO) — 3.3 V or 2.5 V
5V Tolerant I/O — Yes
In-System Programmability — IEEE Std. 1532 compliant
Process Technology — CMOS EEPROM, 0.30 um

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