EPM5032JC25 vs EPM5032JC Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM5032JC25 disebabkan oleh Altera dan EPM5032JC disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EPM5032JC25 | EPM5032JC |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 EPLD |
| Device | EPM5032 | — |
| Logic Elements | 32 macrocells | — |
| Propagation Delay (tPD) | 25 ns | [DATA_NEEDED: specific speed grade value] |
| Maximum Internal Frequency | 62.5 MHz | — |
| Product Terms | 320 | — |
| Flip-Flops | 32 | — |
| Dedicated Inputs | 7 | — |
| Bidirectional I/O Pins | 16 | — |
| Total Inputs to Array | 24 | — |
| Bilangan Output | 16 | — |
| Architecture | PAL-type macrocells with global Programmable Interconnect Array (PIA) | — |
| Technology | CMOS EPROM, UV-erasable (windowed) / OTP | — |
| Tegangan Pemberi Arus | 5 V (TTL-level I/O) | — |
| Kemasan | 28-pin PLCC (JC) | PLCC-44 |
| Jenis Pemasangan | Surface Mount | Surface Mount (J-lead) |
| Status RoHS | [DATA_NEEDED: RoHS status] | unknown |
| Macrocells | — | 32 |
| Logic Gates | — | 600 usable gates |
| Maximum I/O Pins | — | 40 |
| Supply Voltage (VCC) | — | 5 V |
| Input Type | — | TTL-compatible |
| Jenis Output | — | TTL/CMOS-compatible |
| Suhu Operasi | — | 0C to +70C (commercial) |
| Programmability | — | UV-erasable (windowed ceramic) / OTP variants |
| Design Software | — | MAX+PLUS II / Quartus legacy |
| JEDEC Standard | — | JEDEC PLCC-44 footprint |
| Lead-Free | — | unknown |