EPM5064JC vs EPM5032JC-20 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM5064JC disebabkan oleh Altera dan EPM5032JC-20 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EPM5064JC EPM5032JC-20
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Family MAX 5000 MAX 5000
Device Type EPLD (Erasable PLD) —
Macrocells 64 32
Usable Gates 1,250 (approx.) —
Logic Array Inputs 36 —
Logic Array Outputs 64 —
Kemasan 68-pin PLCC (JEDEC) 68-pin JLCC (windowed ceramic)
Jenis Pemasangan Surface Mount (socketed) —
Supply Voltage (VCC) 5 V (typical, 4.75 V - 5.25 V range) —
I/O Logic Level TTL / CMOS compatible —
Configuration Memory EPROM (UV-erasable window or OTP) —
Suhu Operasi [DATA_NEEDED: operating temperature grade] —
Pin-to-Pin Delay (tPD) [DATA_NEEDED: specific tPD grade value] —
Maximum Frequency (fMAX) [DATA_NEEDED: fCNT grade value] —
Status RoHS [DATA_NEEDED: RoHS compliance] —
Lead-Free [DATA_NEEDED: lead-free status] —
Aras MSL [DATA_NEEDED: MSL rating] —
Programming Tool Altera MAX+PLUS II / Quartus II (legacy device support) —
Product Type — UV-erasable Programmable Logic Device (PLD)
Logic Array Blocks (LABs) — 1
Product Terms (P-terms) — 320
Propagation Delay (tPD) — 20 ns
Frekuensi Klock Maksimum — 62.5 MHz
Setup Time — 10 ns
I/O Lines — 16 (bidirectional)
Dedicated Inputs — 8
Total Inputs — 24
Process Technology — CMOS
Erase Method — UV (12V VPP + ultraviolet exposure)
Programming Voltage (VPP) — 12 V
Architecture — PAL-type AND-OR array with PIA interconnect
Status Lingkungan Hidup — Obsolete (legacy Altera MAX 5000)

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