EPM5064LC-1 vs EPM5064JC-2 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM5064LC-1 disebabkan oleh Altera dan EPM5064JC-2 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EPM5064LC-1 | EPM5064JC-2 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Family | MAX 5000 | MAX 5000 |
| Macrocells | 64 | 64 |
| Logic Array Blocks (LABs) | 4 | 4 |
| Usable Gates | 1.25K (approx.) | 1250 |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5 V (4.75 V to 5.25 V) |
| Internal Operating Frequency | 62.5 MHz | — |
| Propagation Delay (tPD) | 40 ns | 45 ns |
| Input Lines | 36 | — |
| Dedicated Inputs | 7 | 7 |
| Output Lines | 28 | — |
| Programming Technology | OTP / UV-Erasable EPROM | — |
| Kemasan | 44-pin PLCC (Plastic Leaded Chip Carrier) | 28-pin CLCC (J-lead, ceramic, windowed) |
| Process Technology | CMOS | — |
| Suhu Operasi | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: commercial or industrial grade] |
| Status RoHS | [DATA_NEEDED: RoHS compliance] | — |
| Programming Interface | JTAG (ByteBlaster-compatible) | — |
| Maximum Clock Frequency (fMAX) | — | 50 MHz |
| I/O Pins | — | 28 |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| Technology | — | CMOS, UV-erasable EPROM |
| Programming Method | — | UV-erase + EPROM programmer (not ISP) |
| Compliance | — | RoHS status unknown (ceramic/J-lead windowed part, legacy product) |