EPM5128LC-1 vs EPM5192-1LC Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM5128LC-1 disebabkan oleh Altera dan EPM5192-1LC disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EPM5128LC-1 | EPM5192-1LC |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Logic Elements / Macrocells | 128 macrocells | — |
| Number of Usable Gates | [DATA_NEEDED: usable gates] | — |
| Dedicated Inputs | 7 | — |
| Bidirectional I/O Pins | 52 | — |
| Total User I/O | 60 (max) | — |
| Propagation Delay (tpd) | 30 ns | [DATA_NEEDED: -1 speed grade tpd in ns] |
| Supply Voltage (VCC) | 5 V (±10%) | — |
| Process Technology | CMOS EPROM, UV-erasable | UV EPROM, erasable windowless |
| Programmability | UV-erasable / OTP (windowed package) | — |
| Package Type | 68-pin J-lead ceramic chip carrier (PLCC windowed) | — |
| Suhu Operasi | 0C to +70C (commercial) | 0C to +70C (commercial) |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| Jenis Pemasangan | Surface Mount (J-lead PLCC socket compatible) | Surface Mount |
| Status RoHS | [DATA_NEEDED: RoHS status] | Non-compliant (ceramic windowless package, lead-bearing termination) |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 3,750 |
| Macrocells | — | 192 |
| Logic Array Blocks (LABs) | — | 4 |
| User I/O Pins | — | 64 |
| Maximum Operating Frequency | — | 62.5 MHz |
| Tegangan Pemberi Arus | — | 5 V |
| Programmable Interconnect | — | PIA (Programmable Interconnect Array) |
| JTAG Boundary Scan | — | IEEE 1149.1 compliant |
| Kemasan | — | 64-pin Ceramic J-Lead Chip Carrier (LC) |