EPM5192GC84-1 vs EPM5192GI84 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM5192GC84-1 disebabkan oleh Altera dan EPM5192GI84 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EPM5192GC84-1 EPM5192GI84
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Family MAX 5000 MAX 5000
Product Type UV-Erasable/OTP Complex PLD (CPLD) —
Technology CMOS (EPROM-cell based) —
Macrocells 192 192
Propagation Delay (tPD) 40 ns (speed grade -1) —
Frekuensi Klock Maksimum 50 MHz —
Supply Voltage (VCC) 4.75 V to 5.25 V —
Dedicated Inputs 7 —
User I/O Pins 64 —
Total Inputs / Outputs 72 inputs / 64 outputs —
Architecture Shared input/clock and shared product terms —
Kemasan 84-pin PGA (Pin Grid Array), WPGA code 84-pin PGA (WPGA, square, through-hole, pin/peg terminals)
Temperature Grade Commercial Industrial
Jenis Pemasangan Through-hole (PGA socket) Through-Hole (PGA socket or PCB pin/peg)
Status RoHS Compliant (per third-party distributor listing) [DATA_NEEDED: most legacy PGA parts are non-RoHS]
Programming Method UV erasure (quartz window) + EPROM programmer —
Logic Element Type Macrocells with AND/OR array —
Device Type — UV-Erasable / OTP Complex PLD (CPLD)
Logic Array Blocks — [DATA_NEEDED: number of LABs]
Package Code — WPGA
Operating Voltage (VCC) — 5 V (typical)
I/O Logic Compatibility — TTL
Programmable Flip-Flop Modes — D, T, JK, SR
Programmability — UV-erasable (windowed) / OTP
Programming File Format — JEDEC map via MAX+PLUS II / A+PLUS
Propagation Delay — [DATA_NEEDED: tPD in ns]
Max User I/O Pins — [DATA_NEEDED: usable I/O count for this package]
Gambaran Suhu Operasi — -40 C to +85 C (industrial)
Lead-Free — [DATA_NEEDED: legacy part, likely contains lead]
Number of Terminals — 84
Terminal Form — PIN/PEG
Package Shape — SQUARE

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