EPM5192GM-1 vs EPM5192GI84 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM5192GM-1 disebabkan oleh Altera dan EPM5192GI84 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EPM5192GM-1 EPM5192GI84
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Family MAX 5000 MAX 5000
Logic Cells 192 —
Propagation Delay (tpd) 55 ns —
Process Technology CMOS —
Programmable Element UV-erasable EPROM —
Kemasan CPGA-84 (Windowed Ceramic PGA) 84-pin PGA (WPGA, square, through-hole, pin/peg terminals)
Kiraan Pin 84 —
Tegangan Pemberi Arus [DATA_NEEDED: VCC nominal] —
Gambaran Suhu Operasi [DATA_NEEDED: commercial/industrial/military grade] -40 C to +85 C (industrial)
Programmable Macrocells 192 —
User I/O Pins [DATA_NEEDED: user I/O count] —
Jenis Pemasangan Through-Hole (Pin Grid Array socket) Through-Hole (PGA socket or PCB pin/peg)
RoHS Compliance unknown (legacy ceramic PGA) —
Lead-Free Status unknown —
Programming Interface Altera ByteBlaster / JEDEC bitstream —
Development Tool Altera MAX+PLUS II (legacy) —
Device Type — UV-Erasable / OTP Complex PLD (CPLD)
Macrocells — 192
Logic Array Blocks — [DATA_NEEDED: number of LABs]
Package Code — WPGA
Operating Voltage (VCC) — 5 V (typical)
I/O Logic Compatibility — TTL
Temperature Grade — Industrial
Programmable Flip-Flop Modes — D, T, JK, SR
Programmability — UV-erasable (windowed) / OTP
Programming File Format — JEDEC map via MAX+PLUS II / A+PLUS
Propagation Delay — [DATA_NEEDED: tPD in ns]
Max User I/O Pins — [DATA_NEEDED: usable I/O count for this package]
Status RoHS — [DATA_NEEDED: most legacy PGA parts are non-RoHS]
Lead-Free — [DATA_NEEDED: legacy part, likely contains lead]
Number of Terminals — 84
Terminal Form — PIN/PEG
Package Shape — SQUARE

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