EPM7128STC100-10 vs EPM7128STC100-15N Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM7128STC100-10 disebabkan oleh Altera dan EPM7128STC100-15N disebabkan oleh Intel. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EPM7128STC100-10 EPM7128STC100-15N
Merek Altera Intel
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Family MAX 7000S MAX 7000S
Device Type CPLD (Complex Programmable Logic Device) —
Macro Cells 128 128
Usable Gates 2,500 2,500
User I/Os 84 —
Logic Array Blocks 8 (16 macrocells per LAB) —
Propagation Delay (tPD) 10 ns —
Internal Counter Frequency (fCNT) 100 MHz —
Logic Family CMOS —
Supply Voltage (VCCINT) 5 V —
MultiVolt I/O Voltage 3.3 V / 5 V —
Kemasan TQFP-100 (C100) 100-pin TQFP
Kiraan Pin 100 —
Jenis Pemasangan Surface Mount —
Programmability In-System Programmable (JTAG, IEEE 1149.1), EEPROM —
Suhu Operasi 0C to +70C (commercial) 0C to +70C (commercial)
Status RoHS [DATA_NEEDED: RoHS compliance status not in provided data] Non-RoHS (legacy SnPb finish typical)
Product Type — CPLD (Complex Programmable Logic Device)
Logic Array Blocks (LABs) — 8 (16 macro cells each)
Maximum User I/O — 84
Pin-to-Pin Logic Delay (tPD) — 15 ns (-15 speed grade)
Maximum Internal Frequency — 76.9 MHz
Supply Voltage (VCC) — 5 V (4.75 V to 5.25 V)
Supply Voltage (VCCIO) — 3.3 V or 5 V (per bank)
Technology — CMOS EEPROM, in-system programmable
JTAG (IEEE 1149.1) — Yes - in-system programming
Output Options — Totem-pole or open-drain (per pin)
Dedicated Inputs — 4 global inputs
Status Lingkungan Hidup — Obsolete (PDN effective 2017-06-01)

Laporan Datasheet & Sumber

Lihat Semua Produk Buat BOQ Minta Bao Harga